| A fundamental hurdle to realizing the exciting future applications of embedded computing is lack of adequate power supply. Unlike the exponential growth in computing capability, the improvements in power sources have been lackluster. Technology scaling, driven by Moore's law, has produced smaller devices that can operate on lower supply voltages; but as a side effect, nanoscale devices are becoming increasingly unreliable. The resulting increase in transistor density further exacerbates the power problem. Therefore, the computing industry faces a pressing need to aggressively reduce power consumption and efficiently address error resiliency.;Conventional approaches to error resiliency using redundant computations have incurred the associated overheads of power and silicon area. Traditional power reduction techniques scale supply voltage or clock frequency to adapt to changing demands of the application, while being limited to ranges where computation is free of error. Addressing in isolation the related problems of power reduction and error tolerance may fail to produce the gains required by future systems. It may be desirable to allow occasional hardware errors for the sake of power savings; however, this trade-off must be done without adversely impacting the end-user experience.;Many applications in signal processing, communications, and multimedia already allow several forms of noise, such as additive environmental noise, interference, and quantization. This research views hardware error as a new source of noise that is analogous to traditional forms of noise. In so doing, it enables dynamically trading-off reliability for power savings while meeting application performance requirements.;Our estimation-theoretic framework is a mathematical formalization that allows us to state system-on-chip (SoC) design problems as constrained optimization problems. The engineering constraints, such as hardware availability and cost, are explicitly captured as design constraints. By accounting for application-level performance requirements, the framework provides a notion of power, reliability, and performance optimality of the design. The mathematical abstraction of the framework results in different particular design techniques depending on the nature of the application. We have identified four classes on the basis of these design techniques, and described applications typical of each class.;For parallel and heterogeneous systems, an estimation-theoretic redesign resulted in a 30%--40% power reduction in wireless and video systems. The application-awareness characteristic of estimation-theoretic SoC design can also be adopted in designing general-purpose processors. By exposing architectural diversity and controlled hardware errors in logic, the stochastic processor proposed here allows dynamic power reduction of about 20%--60% in the motion-estimation block of a video communication system.;In addressing power/reliability problems of general parallel SoCs, we have also identified an important robust estimation problem that has remained largely unaddressed within the robust statistics community. To address this need, new methods for robust estimation with correlated observations were developed that could be applicable to more general estimation problems. |
