Power dissipation and state variables for information processing

Over the past half century, the amount of information that computers are capable of processing (functional throughput) has followed the well-known Moore's law or doubled every 18 month. This year, the most advanced silicon manufacturers has moved to the 65-nm node with a physical gate length about 30 nm. Such scaling will continue over the next decade and, according to the ITRS 2007 Roadmap, CMOS will reach the 18-nm technology node or 7-nm physical gate length by 2018. There are many technological challenges arising while industry approaches the 18nm node. One of the major issue in information processing is power dissipation. CPU power density has experienced an exponential growth rate with a feature size miniaturization. In this work we consider the basic power dissipation in the information processing. First, two approximations for sudden and quasistatic switching are addressed. Then the relation between power dissipation and switching speed for the general two levels switch is derived and the optimal drive function is found. State variables for information processing are discussed. We show that spin waves can be efficiently utilized for both conventional and classical computing. In classical computing spin waves can be efficiently employed for highly scalable and low power dissipation information processing. "Spin Wave Bus" for quantum computing gives an opportunity to perform single qubit and two qubits gates in much more efficient ways than conventional approaches for solid state quantum computing.