Digitally controlled DC-DC buck converter utilizing sigma -delta frequency discriminators

The power management system became an integral part of the design of any portable device (such as PDA) as the need for extending battery life became a hard requirement. Most power management systems include some type of step-down (buck) DC-DC converters along with Low-Drop-Out (LDO) regulators and possibly step-up (boost) converters.;This work presents a novel 0.18 mum CMOS digital control architecture for a DC-DC buck converter. A digitization technique based on non-feedback SigmaDelta frequency discriminators (NF-SDFD) and a hybrid segmented digital pulse width modulator (SDPWM) in the feedback loop of the converter are utilized. The NF-SDFD is built using a pure digital complementary metal-oxide semiconductor (CMOS) circuit with a small number of components (2 D-type flip flops and an XOR gate). The resolution of the analog-to-digital (ADC) is 8-bit after decimation. The 9-bit hybrid SDPWM is built from a 4-bit charge-pump based DLL for fine resolution and a 5-bit counter for coarse resolution. Both ADC and SDPWM blocks have been implemented with almost all digital CMOS. Additionally, these blocks consume less power, have lower complexity and ease of scalability compared to the previous state of the art techniques used to build digital controllers. The proposed system is built using 0.18mum, single-poly, 6-level metal CMOS process. The overall die characterization results are as follows: 460 quiescent current, 14 mV output voltage ripple, and 130 mV output voltage droop with 300 mA transient current and 100 muS settling time. A regulated output voltage accuracy of 1% and maximum efficiency of 94% is achieved. The chip is fabricated in a 0.18microm, single poly 6-level metal CMOS process utilizing area of 2.25 mm2 (1.5 mm x 1.5 mm).