Design for reliability: From silicon characterization, model calibration, to efficient simulation

Process variation and aging degradation have emerged as the most prominent problem in deep nanometer technology as complementary metal-oxide-semiconductor (CMOS) scaling continues. Design consideration for reliability, especially at an early stage, is added to the design flow to help reduce design cycle, improve design margin and increase product yield. This new design flow currently faces the challenges of model accuracy and simulation efficiency.;Test structures are developed to characterize the variability and degradation on silicon. Negative Bias Temperature Stability (NBTI) is the dominative aging mechanism below 45nm technology due to the fact that the oxide thickness has been pushed to its limit. Due to the unique stress-recovery mechanism of NBTI, an on-the-fly structure is necessary to test and validate the aging degradation close to the realistic environment. Limited by the closed-loop structure, traditional frequency output ring oscillator (RO) based test structure lacks the flexibility for tuning the stress condition. In addition, the logic path in real circuit may be exposed to a different operation sequence from the test RO, leading to variations in the degradation rate. To overcome these problems, a novel test structure that directly measures the delay change, which is integrated with a high resolution Time to Digital Converter (TDC), is presented in this dissertation work. The open-loop structure and the test array of data paths further provide the convenience to characterize the aging degradation for all types of circuit topologies and operations.;Reliability simulation is usually done through aged SPICE model. The simulator calculates circuit node activity based on the input stimulus pattern and re-run the simulation with aged parameters. The speed of transistor model therefore greatly limits the simulation efficiency and tool capacity. A Finite-Point (FP) transistor model is further developed to improve the simulation speed in the presence of variations and aging degradations. For both the I-V and C-V characteristics of a transistor, data points are identified based on their physical meanings and their importance in circuit operation. The impact of design variations and aging degradation is embedded into these key points using simplified analytical expressions. This novel approach significantly enhances the simulation speed with sufficient accuracy. Compared to BSIM based SPICE model, the simulation time can be reduced by 7 times in transient analysis and more than 9 times in Monte-Carlo simulations.