Research On Performance Optimizing Techniques For Microprocessor On-Chip Memory System

The development of the Very Deep Submicron IC manufacturing technolgy provides a growth space to IC design technique.The number of the transistors integrated in a single chip has reached billion-level.It is expected that this number will exceed 18 billion in 2020.At present,the advance microprocessors produced by IBM and Intel have integrated more than 3 billion transistors.Large and multi-level Cache has been adopted in all these high-performance microprocessors,in order to hide the latency,while the Cache has occupied the 60%-70% of the whole chip area.The continuous driving of various application requests and promoting of computer architecture design technique put forward higher requirements and severe challenges for microprocessor on-chip memory system.The “Memory Wall” problem obstructs the improvement of overall processor performance.So how to make a reasonable,efficient and intelligent use of the Cache space on chip,and build a highperformance memory system,and then cross the “Memory Wall” is an important research subject on the microarchitecture of the processor.This paper analyzed the main factors affecting the performance of processor memory system deeply,and had an intense study on key techniques for on-chip memory system's performance optimization.We believed that the pollutions brought by the speculative execution on the path of branch prediction caused a negative impact on space utilization of Cache and processor IPC performance.However,the existing Cache control mechanisms are short of the ability to relieve Cache pollutions and make use of data prefetching effect from speculation path efficiently,the improvement on Cache performance is hindered.In addition,there are few relative studies on the low latency Cache replacement algorithm,which still have further optimizing space.In this paper,based on the main factors of impeting the promotion on processor memory system,we had a further study on optimizing techniques for processor memory system,from pollution reducing,usage efficiency improvent of Cache space and low latency Cache replacement algorithm,the main works and innovations are as follows:(1)Proposing a D-Cache pollution filter scheme Based on memory access tracing of branch speculative path,by use of memory access tracing chart which formed dynamicly from branch speculative path,it has the real-time tracking to the data written in Cache by memory instruction,and also adds address Tag field with SDT(Speculative Execution Data Tag)and SPN(Speculated Path Number),in order to cooperate memory access tracing chart from branch speculative path to realize DCache pollution control,its advantages are embodied in reducing the impact to the Cache efficiency when the data was written into Cache by the memory instruction from the speculative path,increasing the Cache space utilization,and decreasing the design complexity,especially for the small Cache.The experiment results show that,this scheme increases the L1 D-Cache hit rate from 0.03% to 6.69%,averagely 1.80%;and improves the IPC from 0.01% to 6.60%,averagely 2.56%.(2)Proposing a low pollution Cache access scheme based on valid-bit splitting of Cache data address tag,through the optimizing for valid-bit in the data address tag,which is substituting two bits flag-RVB(read data valid bit)and WVB(write data valid bit)for the original one bit address tag,and make a special control on the reading and writing operation to Cache data lines,according to the different RVB and WVB combinations.Firstly,the strategy could distinguish access memory instruction between the correct path and the speculative path,and process it in different ways;Secondly,the strategy is capable of retaining and utilizing the possible data prefetching effect brought by data access on speculative path;Thirdly,when writing data to Cache,it is possible to write data to Cache lines directly by substituting for the speculative Cache data without Cache replacement algorithm.It contributes to the improving of Cache space utilization and the efficiency of reading and writing,and it also have an effect on decreasing the influence to the on-chip memory system caused by speculative path data accessing.Simulation result indicates that,the strategy can increase IPC 4.04%,and reduce the miss rate of D-Cache 29.66% averagely.(3)Proposing a Cache Space Pre-Ordering algorithm,called CSPO,provides space pre-ordering mechanism for Cache,which includes pre-ordering space counter(POC),Cache line pre-ordering tag(POT),Cache pre-ordering address register(CPAR),and corresponding Control logic,and realize the parallel execution of Cache replacement target selection and external memory accessing.This algorithm also has the ability to write Cache dirty data back in advance as soon as possible,which hides the latency produced by Cache replacement operation and Cache dirty data write-back,reduces the total latency of the memory instruction processing,and improves IPC of the program execution.Especially for the case when the pre-ordering Cache-line is dirty,CSPO can initiate the write-back operation of dirty data in advance,and significantly reduce the total latency of memory access.Simulation results show that CSPO scheme can increase IPC by an average of 5.37%.The research in this paper provides a useful reference to optimize the on-chip memory system performance,and also a method and technique for the further improvement of Cache in the advanced processor architecture.