Design Optimization Techniques For Resource-Constrained Safety-Critical Real-Time Embedded Systems

Real-time embedded systems are used in a wide range of industrial applications.This thesis focuses on safety critical applications such as automotive and avionics systems.Taking automotive systems as an example,the trends of electrification,intelligence and automation of next generation automobiles have led to an increase in the scale and complexity of Automotive Electrical/Electronic(E/E)systems.Modern Automotive E/E system of a high-end vehicle has become a complex distributed system consisting of tens or even hundreds of Electronic Control Unit(ECU)nodes connected by multiple buses with different networking protocols.Design,analysis and development of such systems are highly challenging,and need to consider a variety of requirements and constraints,including: multiple applications of different safety levels co-exist in a single system,forming a Mixed-Criticality System that needs to pass multiple levels of safety certification;system hardware resources are constrained due to cost and power consumption constraints;safety critical applications have hard real-time requirements,and deadlines must be strictly met;safetycritical applications require high reliability and fault tolerance,especially regarding soft errors that are common in harsh operating environments;integrated heterogeneous hardware platforms require high-performance,low-power hardware coprocessors to accelerate the real-time operation of deep learning and other algorithms.In response to these challenges,this thesis proposes a series of design optimization algorithms,including:· Safety-critical real-time embedded systems must satisfy dual requirements of fault-tolerance and real-time predictability.Control Flow Checking(CFC)is an effective technique for improving embedded systems' reliability by online monitoring and checking of software control flow to detect runtime deviations from the control flow graph.However,inserting instrumentation code in every basic block incurs significant execution time overhead,which may cause the program to violate its timing constraints.In this thesis,we propose Worst-Case Execution Time(WCET)-Aware Partial Control Flow Checking(WAPCFC),which selectively instruments a subset of basic blocks or super-nodes in order to make the program partially resilient to control flow errors while keeping the program WCET below a given upper bound.WAPCFC makes control flow checking algorithms suitable for resource-constrained safetycritical real-time embedded systems,and enables designers to make trade-off decisions between real-time and reliability requirements.· The AUTOSAR model of software in automotive electronics typically consists of multiple Soft Ware-Components(SWCs),which are to be mapped by the designer to a distributed hardware platform with multiple ECUs connected via an in-vehicle network.As the number of SWCs and ECUs in vehicles systems grows rapidly,it becomes infeasible to find optimal solutions by hand.In this thesis,we propose an optimization algorithm for implementing AUTOSAR models on in-vehicle distributed embedded systems,with the goal of minimizing bus utilization while ensuring system schedulability,and memory overhead of data consistency mechanisms on each ECU.· Time-Triggered Protocol(TTP)is an industry-standard bus protocol widely-used in safetycritical avionics distributed embedded systems.Design space exploration for TTP-based distributed embedded system involves searching through a vast design space of all possible task-to-processor mappings and bus access configurations.In this thesis,we propose an optimization algorithm for distributed embedded systems based on Logic-Based Benders Decomposition,with the goal of minimizing bus utilization,and efficiently utilizing bus bandwidth while meeting the end-to-end deadlines of a TTP-based distributed system,by optimizing task-to-node mapping and TTP bus access configuration.· We consider Spiking Neural Network(SNN)for application modeling of high-performance hardware accelerators for Deep Learning.An SNN can be trained in directly by ANN-toSNN conversion,i.e.,first training an Artificial Neural Network(ANN)with the conventional backpropagation algorithm,and then converting it into an equivalent SNN.Most ANN-toSNN conversion techniques either adopts rate coding,where the number of spikes used to encode an activation grows linearly with the activation value,or rely on computationally intensive spiking neuron models,which integrate input spikes using complex arithmetic operations,thus incurring high computational cost.To reduce the computational cost of the resulting SNN and to improve the efficiency and performance of neural network accelerators,we propose an ANN-to-SNN conversion algorithm based on Logarithmic Temporal Coding(LTC),where the number of spikes used to encode an activation grows logarithmically with the activation value,thus reducing the number of spikes in the SNN.The accompanying Exponentiate-and-Fire(EF)neuron model to be used in conjunction with LTC only involves efficient bit-shift and addition operations,which reduces the computational cost of the neuron's integration of each input spike.Moreover,we improve the training process of ANN to compensate for approximation errors due to LTC,reducing the performance gap between the resulting SNN and the original ANN.The series of algorithms developed in this thesis provide design-stage algorithm support for nextgeneration highly-complex and resource-constrained safety-critical real-time embedded systems.