Research On Key Technologies And Circuit Design Of Ultra-Low-Power On-Chip Power Management For Self-Powered Internet-of-Things Node

In recent years,the rapid development of wireless internet of things(IoT)equipment like wireless sensor nodes,wireless healthcare devices,and portable electronic products have led to power management system development on ultra-low power(ULP),high efficiency,and high integration.To keep the battery and(or)energy harvest powered system stably operating for longer than 10 years.ULP system design technique is required.IoT power management system also require high power conversion efficiency and high power density.Power management unit(PMU)integrated several channels and several types of power converters in a signal chip,thus it reduce the total power loss,off-chip components,total solution size,and cost.To optimize the power management system of self-powered IoT node,this thesis focus on key technologies,system design,and circuit design of ULP power management system.The analysis on the power loss of IoT node shows that the system's average of power loss is only serval macro watt.The power management system's quiescent current should be sub-?A level.Thereby,thesis study the key technologies and implementation methods of basic ULP blocks.Based on the study of MOS operating behavior in sub-threshold region,several basic function blocks' principle and implementation methods are descripted,including native NMOS current reference,zero temperature coefficient current reference,ULP bandgap,sub-threshold voltage reference and sample/hold voltage reference.To reduce the interference from noise,new structure isolation ring,layout floorplan,and package are introduced.A "floating isolated" guard ring is proposed to reduce the interference of power stage noise which is generated by switching node so called minority injection.Benefit from those new techniques,the ULP circuit and power stage can be integrated in a signal chip.In order to increase the power converter's conversion efficiency from macro amper load to mili amper level load,an adaptive bias current pulse frequency modulation(PFM)ULP step down switching power converter is proposed.The power converter can dynamically enable or disable circuit blocks expect "always on" ULP circuits.The system turn-on the large quiescent current blocks only when the power stage is turn-on.The proposed novel structure of PFM comparator could adaptively adjust its bias current depend on the frequency of PFM.Sample/hold voltage reference has less than 1.5%voltage error with 20 nA quiescent current By using 0.35 ?m standard CMOS technology,a 95 nA quiescent current step down power converter is proposed.The power converter is implemented and verified by simulation and test.The ULP converter achieves conversion efficiency of 79.8%at 2?A load,regulating output at 2.5 V with a 3.6 V supply.Compared to published researches,the proposed ULP power converter has lower quiescent current and higher efficiency.Ultra long battery life and 3G/4G high speed data transfer system requires higher input voltage and higher integration.However,the ULP design is a challenging task in a wide input voltage system.This thesis studied wide input voltage range self-powerd IoT system,and proposed a ULP PMU.The proposed PMU integrated several channels.Those channels share the ULP auxiliary blocks and the quicent current is significantly reduced.The PMU includes an adaptive bias current PFM mode ULP power converter for improving efficiency at light load and a pulse width modulation(PWM)mode power converter for increasing the output power capacity.Fully integrated high voltage level-shift and drivers without off-chip components and extra pins are proposed.The novel high voltage power stage increases the PMU integration while it reduces the power rail "bouncing" during power stage switching The wide input voltage fully integrated ULP PMU is implemented and verified in CMOS based high voltage Bipolar-CMOS-DMOS(BCD)process.The silicon test results shows that the PMU's quiescent current is 550 nA,and the conversion efficiency is larger than 50%at 2 ?A load The ULP converter's load current is up to 50 mA with maximum 87%efficiency.The PWM mode converter's load current is up to 500 mA with 90%efficiency.The ULP PMU could reduce the wide input voltage power managmenet system's Iq from macro amper level to nano amper level.The self-powered device's life time can be signifcatly increased by using the proposed PMU.