| Wireless Sensor Network(WSN) is used to sense, process, and transmit various environment information in the area where the network is distributed, like temperature, humidity, pressure, illumination, airspeed, etc. Due to its flexible distribution network, long lifetime, strong privacy, and high fault-tolerance, WSN has been widely used in the areas of health care, agriculture, smart home and intelligent building, fire rescue, military, and marine monitoring. However, since the network nodes are long exposed in the external environment and each node's resource is limited, the WSN is still facing with the problems of cost, power and safety. In order to reduce the cost and power of WSN, this paper is devoted to optimizing the wireless transceiver in the levels of architecture and specific circuit. In terms of security, this paper also studies the method of protecting the wireless transceiver chip in the circuit and layout level.Firstly, a new low-IF wireless transceiver architecture suitable for On/Off Keying(OOK) modulation is proposed. The basic idea of this architecture is to filter the IF signal in both the analog and digital domains. In the analog domain, the IF signal is compared with a threshold voltage, and further amplified to rail-to-rail digital signal. While in the digital domain, the rail-to-rail digital signal is filtered by countering the number of the pulses in a certain time. The anti-noise performance of this receiver is enhanced and the required input Signal-to-Noise Ratio of the baseband demodulator is less than 6 d B. Moreover, the baseband demodulation circuit is relatively simple and no Automatic Gain Controller is needed, which hence decreases the total power and area consumption of the transceiver. The theoretical analysis result and MATLAB simulation result of the received bit error rate show the effectiveness of the proposed transceiver structure.Secondly, low-cost specific circuits of the wireless transceiver are designed. In order to reduce the area consumption of the chip, the RF front-end circuits are implemented without on-chip inductors. The Low Noise Amplifier(LNA) is based on inductorless wideband structure, the Power Amplifier(PA) adopts bond-wire inductor to realize output impedance matching and frequency selection, and the Phase Locked Loop(PLL) uses ring oscillator to generate the local oscillation signals. Moreover, a novel 10 MOS linear voltage-to-current converter used in the PLL block is proposed. The voltage-to-current converter does not use any resistor and amplifier, which will decrease the complexity and hence the area consumption of the PLL. Multiple on-chip linear low dropout regulators are also used to supply each block respectively, thereby decreasing the peripheral devices outside the chip. In order to reduce the power consumption, the power management for the whole chip is first realized. Furthermore, for the power-hungry part of the PLL, high-speed 2/3 Prescaler, a new structure which only utilizes five NMOS-like blocks is proposed to achieve both low power consumption and wide operating frequency range. The 16/17 Prescaler utilizing this novel 2/3 Prescaler achieves operating frequency range of 0.5-8 GHz while its maximum power consumption is decreased to 0.8 m A.Then, an image rejection filter, a hard decision circuit, reference power supplies, and a digital baseband demodulator circuit are designed. Since the inductorless wideband LNA nearly has no capability of image rejection, an image rejection filter based on Nauto inverter Gm cell is developed to suppress the image interference signals. An offset-canceling hard decision circuit is used to amplify and filter the IF signal. The reference power supplies contains power management, bandgap voltage reference, digital-type and analog-type linear low dropout regulators, reference voltage generating circuit and bias circuit, all of which are used to realize the power management and to provide the process-, temperature-, and voltage-consistent power supply and bias for the whole chip. The OOK digital baseband demodulator circuit based on pulses counting is used to convert the IF signals to the RX data.Finally, the chip-level security of the wireless transceiver is realized. The main idea is to use Advanced Encryption Standard(AES) cipher algorithm and switched-capacitor Physical Unclonable Function(PUF) to prevent external non-invasive, semi-invasive and invasive physical attacks. In particular, a wireless transceiver security architecture based on AES cipher algorithm and PUF is first proposed to realize the physical level protection of the wireless sensor node. Then, a switched-capacitor PUF is developed to provide stable and randomly distributed keys for AES encryption and decryption. Furthermore, the combine of switched-capacitor PUF's capacitive sensitivity with random resetting technology will make the whole wireless transceiver chip invasive-attack-resistant and semi-invasive-attack-resistant. Compared with the existing chip security shields, the proposed security design has higher and more stable anti-invasive-attack sensitivity, it can detect a capacitor variation of 2.65 f F caused by outside physical attacks.The simulation results show that the proposed novel OOK wireless transceiver can transmit and receive data properly. Its area consumption is about 2.8 mm2, and the power consumption is 7.6 m A and 7.06 m A for transmitter and receiver respectively, which realizes both low cost and low power. The test results show that the proposed chip-level security-protecting scheme can effectively prevent external physical invasive attacks, thereby ultimately achieving secure data transmission in WSN. The results of this thesis have positive theoretical and practical significance in the development of low-cost and low-power wireless transceiver design and chip physical protection design. |
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