Studies On Reconfigurable Wireless Intelligent Video Surveillance Platform

With the rapid development of information technology, VLSI manufacturing technology, guided by Moore’s Law, is promoting electronics industry with booming computing capabilities. In this context, intelligent video technique becomes a hot issue along with the progress of computer vision technology. Intelligent video surveillance system came into being based on the application of security surveillance and traffic control. By separating foreground from background and continuous analysis in a specific area, intelligent video surveillance technology is able to get the obscure information from the captured video image and thus can avoid the explosion of information in traditional video applications. Intelligent video surveillance depends on accurate and reliable video analysis algorithms. These algorithms have to process large amounts of data and consume quite a lot of computing resources, which brings a huge challenge to real-time video processing. DSP-based video surveillance system is flexible and simple to implement, but the performance is not optimistic when processing hundreds of video streams. However, in distributed intelligent video surveillance system, ASIC chips as video analysis engine, guarantees good real-time performance, but suffers from the poor flexibility. In this thesis, considering both computing performance and flexibility, the author makes use of FPGA’s partial dynamic reconfiguration technology to carry on the study of reconfigurable wireless intelligent video surveillance platform, which can be divided into following parts.1) Xilinx FPGA partial dynamic reconfiguration technology has been studied. A FPGA-based reconfigurable video processing hardware platform which can be reconfigured through wireless connections in runtime has been proposed. The platform use an efficient ICAP controller as reconfiguration engine and only a few milliseconds or even tens of microseconds are needed to complete the process of reconfiguration.2) Various algorithms on intelligent video surveillance have been studied and implemented in FPGA, including motion detection, object recognition and object tracking. These video processing modules form the library of hardware intelligent video processing IPs. In motion detection, an improved frame differing method is used; in object recognition, a simplified self-organizing map is presented; in object tracking, an improved color-based particle filter is proposed. All these intelligent video processing IPs perform well and are implemented on FPGA.3) The high performance on-chip communication architecture for intelligent video processing has been studied. The author proposed a4-ary tree based network on chip with good scalability and flexibility which can save quite a lot of traffic load and consume less system power in communication.4) A wireless intelligent video surveillance network named AdVision has been implemented, in which both IEEE802.11and IEEE802.15.4protocols are supported. In the wireless surveillance network, AdNode and AdBridge’s hardware circuits are carefully designed to meet the requirements of both high performance and low power. To realize robust and real-time transferring, AdVision uses a low complexity compressing scheme through prioritized JPEG encoding.