EMC Susceptibility Mechanism Study Of Low-dropout Voltage Regulator | | Posted on:2014-10-15 | Degree:Doctor | Type:Dissertation | | Country:China | Candidate:J F Wu | Full Text:PDF | | GTID:1262330422974279 | Subject:Information and Communication Engineering | | Abstract/Summary: | PDF Full Text Request | | In recent years, the CMOS technology has changed from ultra deep submicron tonanometer. With the decreasing of semiconductor feature size and the increasing ofon-chip clock frequency, there come serious Electromagnetic Compatibility (EMC)problems like simultaneous switching noise, on-chip inter-disturbance, parasitic effectsand so on. The IC’s electromagnetic susceptibility (EMS) has become the bottleneck ofthe electron system performance improvement. This paper studies the failure modes andmechanism of the linear low-dropout (LDO) voltage regulator under ElectromagneticInterference (EMI) and evaluates the defect influence to circuit system. Thesusceptibility performance of the LDO regulator in ageing process is measured byInternational Electrotechnical Commission (IEC) standard test methods in the frequencydomain. The analysis is mainly focused on identifying failure modes, failure mechanism,modeling and prediction by simulations. The failure mechanism is validated bysusceptibility modeling and simulation results.In the first part of the thesis, the LDO susceptibility mechanism and analysismethods are studied. Firstly, the structure of power regulator circuit is analyzed to findthe advantages and disadvantages of LDO regulator. Then, the typical structure of LDOvoltage regulator circuit is divided into operational amplifier, bandgap voltage referencecircuit and pass devices for immunity failure mechanism analysis. The current modelingand simulation methods which are applied in IC EMC research are reviewed. The twokinds of modeling and simulation analysis methods including the circuit level andbehavioral level are mainly analyzed for LDO regulator study. And the direct powerinjection (DPI) method is selected as the test technology to help the mechanism analysis,modeling and simulation process.In the second part of the thesis, the LDO regulator sensitivity circuit levelmodeling and simulation method is evaluated. The structure of a test chip designed byFreescale90nm technology is analyzed firstly. Based on the on-chip voltage sensorasynchronous and synchronous acquisition principle study, an innovative on-chipvoltage test method is presented. Subsequently, the DC functional, impedance andsusceptibility measurement results are explored. The LDO regulator immunity circuitlevel modeling and simulation flow is presented combined with simulation and on-chiptest results. Finally, four types of models from simple to complex levels are discussedstep by step to distinguish contributions of key sub-circuits and parasitic elements in thefrequency domain from1MHz to1GHz.In the third part of the thesis, the LDO regulator susceptibility behavioral levelmodeling and simulation method is evaluated. The structure of an industry test chip isanalyzed firstly. With the test circuit PCB board and impedance calibration board, the immunity measurement environment is built. The test results of DC, impedance and DPIconducted immunity show the DC characteristic, active and passive impedance andsusceptibility level. In modeling process, the non-linear behavioral is proposed fromsimple linear model and linear behavioral model. The simulation results achieve a goodmatch with the test results in the frequency domain.Finally, this paper analyses the drift in LDO immunity after accelerated ageing. Alarge number of measurements which show the variations in the test results for DCcharacteristic, impedance and immunity reveal increasing susceptibility after electricalaccelerated ageing. With the susceptibility drift mechanism study, the immunitydecreasing in ageing process is explained by mathematical analytical analysis of theop-amp input PMOS differential pair. In ageing process, the increasing of NMOSthreshold voltage leads to the decreasing of LDO regulator output voltage. And the biascurrent decreasing is mainly responsible for the immunity decreasing. The regulatoraccelerating ageing model which is combined with reliability and immunity model isestablished to realize the susceptibility level prediction of the entire life cycle. | | Keywords/Search Tags: | Integrated Circuit, Electromagnetic Compatibility, Electromagnetic Susceptibility, Low-dropout Voltage Regulator, FailureMechanism, Modeling and Simulation Methods, On-chip Voltage Sensor, Non-linear Behavioral Model, Threshold Voltage | PDF Full Text Request | Related items |
| |
|