Research On Interface ASIC For High Order SIGMA DELTA Accelerometer

Micromachined accelerometers are currently the most widely used EMESintegrated sensors due to their substantial military and civil value. Among them,Sigma Delta capacitive micoromachined accelerometer, with its large band width,direct digital output, and high compatibility with standard CMOS process, hasattracted considerable attention in the exploration of integrated micro-accelerometer.The research on Sigma Delta micro-accelerometer is of great significance andpractical value, for the key of accelerometer performance lies in its interface ASICcircuit.At present, there are still some aspects to be improved in the research ofhigher-order Sigma Delta interface circuit of micromachined accelerometers, suchas system parameter design, non-linearity analysis, residual motion noise analysisand system optimization. In view of above situations, several key issues about thedesign process of higher-order Sigma Delta micromachined accelerometers arestudied in this paper.Through the comprehensive analysis of features between two higher-orderSigma Delta accelerometer topologys which are single feedback and distributedfeedback, the distributed feedback topology is selected in this paper, and accordingto the structure, a design method of initial system parameter is presented, and thismethod is able to simplify the design procedure efficiently. According to the featureof higher-order distributed feedback digital accelerometers, the system noisetransfer model with considering characteristics of signal transmission is established,and the system non-linear model Combined variety of non-linear sources isachieved. Meanwhile, the relationship among the noise characteristics, thenon-linear characteristics and electrical parameters of system is analyzed based onthese models. The result shows that the optimized performance of digitalaccelerometer can be achieved by tuning system parameters. Residual motion is themost significant distinction between analog closed-loop feedback accelerometer anddigital closed-loop feedback accelerometer, However, there has been no certainconclusion so far in any related references as to whether the residual motion noise isthe main cause of system noise. The analytical model of the residual motion noise is established in this paper. Based on the model, the simulation result suggests thatresidual motion noise is not the main noise source of accelerometers.For the deficiency in the parameter design of traditional Sigma Delta microaccelerometer, which only quantization noise characteristic is taken into account,the combined accelerometer system parameter optimization model is built and theoptimization method is given through comprehensive analysis of system parameters’impact on noise characteristics, nonlinear, stability of accelerometer. The simulationand experimental results indicate that established parameter optimization model andmethod can effectively achieve the optimization of the performance ofaccelerometer.The design of higher-order Sigma Delta interface for micro-accelerometer iscompleted based on theoretical analysis. The circuit structures of analogclosed-loop feedback accelerometer and digital closed-loop feedback accelerometerwhich are composed of adjustable external components are designed. A systemworking mode and control sequence are designed, which basically realizes thesequential separation between the preceding stage weak capacitance detectioncircuit and cascaded integrators. A modified cascaded integrator is designed toeffectively solve the problem in the design of operational amplifier in the integrator.An improved distributed feedback parameter control circuit is designed, combinedfeed-forward gain adjustment circuit, which achieves later adjustment ofaccelerometer system parameters. After the completion of the design including threekinds of op amp, latched comparator, timing generation circuit, voltage referencesource, LDO and other circuit modules, the whole circuit is simulated based on theCadence APS high-speed parallel simulator. The results of simulation show that thetransistor level circuit meets the design requirements.After the layout design of interface chip of the accelerometer, the ASICs arefabricated with the HIT MEMS center engineering batch of wafers. The testingsensor is composed by the chip sample and sensing structure with mid-accuracyfrom Peking University. The measurement results show that every module in thechip works normally. The setup time of comparator is24ns. The temperaturecoefficient of the voltage reference is8ppm/℃. The output noise of LDO is about100nV/Hz1/2. The output noise of analog closed loop accelerometer composed byASIC interface chip and sensing structure is approximately12μg/Hz1/2. The bias stability is0.128mg. The linearity is about0.07%. The digital closed loopaccelerometer that consists of ASIC interface chip and sensing structure is able toachieve optimization of performance on the basis of the established parameterintegrated optimization model. The optimized closed loop output noise is16.9μg/Hz1/2，the linearity is0.085%，achieved moderate accuracy.The theoretical study in this paper is of great significance in guiding thedevelopment of interface circuit of higher-order Sigma Delta capacitive microaccelerometer. The ASIC chip designed and manufactured is of great practicalvalue.