Investigation Of ESD Protection Circuit And Optimization Design Of RFIC

Due to the unique characteristics of radio frequency integrated circuit (RFIC), suchas the sensitivity to noise figure, requirement of good match and gain, different withordinary analog/digital integrated circuits, its electrostatic discharge (ESD) protectiondesign has become more complex and difficult. This dissertation studies the ESDprotection design of RFICs, and the optimization of the above two in condition of deepsub-micron CMOS technology. The content includes the construction of ESDsimulation testing platform, the improvement of device structure, the analysis of ESDprotection with matching network, co-design method of ESD devices with RF circuit,and how to eliminate the impact of ESD structure on the circuit. The major researchwork and results are as follows:1. In this dissertation, the characteristics of several ESD protection devices arestudied and compared, and the LVTSCR device which has a simple structure, lessparasitic effects, high discharging efficiency and easy-adjust switch parameters, isselected. In simulation, the novel carrier transport model and collision ionization modelare used to analyze of the carrier transport characteristics of deep submicron devicesunder ESD stress. With the TLP simulation test platform, the working principle andcharacteristics of the LVTSCR under90nm process are discussed, and the impact ofseveral parameters on the LVTSCR’s snapback characteristic is analyzed. The resultsshow that the turn-on voltage of LVTSCR is less than4V in this dissertation, which issimilar with the ggNMOS results under the same process, while its hold-on voltage ismuch lower than the latter (1.1V to3.3V). Therefore, the LVTSCR has higherdischarging efficiency, which is suitable for input protection of RFICs. The method alsoprovides a good reference and basis for TLP testing and standardization.2．Based on the electrical characteristics of LVTSCR, the impact of the differentbias mode on the switching characteristics is analyzed, and the structural improvementsare presented. For the small turn-on resistance and low hold-on voltage, the SCRdevices in applications are tend to cause latch-up of circuit, or ESD structure unableturning itself off when ESD event is over. Increasing hold-on voltage means increasingthe turn-on resistance, thus several measures are used to increase the current path instructural improvements of LVTSCR, and a double-vertical-trench structure is proposed to limit the current, which obtains good results and occupies a small chip area. Then therelationship of trench depth with hold-on voltage is analyzed, and the bottleneck of thismethod encountered is discussed. The results show that the device is improved tomaintain a hold-on voltage above1.5V, which allows the device to meet the ESDprotection requirements of most of the deep sub-micron low-voltage applications.3. For the lack of ESD device models (including high stress model and small-signalmodel) in existing RFIC techniques, the equivalent method in RF-ESD analysis ignoresa lot of parasitic effects, which results in performance degradation of the core circuitand optimization difficulty when ESD protection is added, especially in high frequency(>5GHz) applications. The subtle change of the parasitic effects may cause themismatch of terminals, degradation of noise figure or gain. Therefore, a method toquantify the ESD structure accurately and introduce it to RF design is presented, whichincorporates the device-level simulation with the device-circuit mixed-mode simulationand high-frequency simulation. In this method, the approach of extracting S-parametersof ESD matching network and establishing table-lookup model to introduce in RFdesign is first used, and all the small-signal parasitic effects of ESD structure are takeninto account, thus accurate simulations can be done and the RFIC performance isoptimized. A5.25GHz narrow-band LNA-ESD design, combined with two-stageone-directional/dual-directional ESD protection based on LVTSCR, is used todemonstrate the feasibility of this co-design method. The RF performance of LNAbefore and after optimization with different ESD protection is discussed. Comparedwith two-stage one-directional ESD protection based on ggNMOS in the literature, theHBM protection level in this work is doubled with the device in same size.4. Using the feedback compensation circuit used in power supply, the originalsignal and the feedback signal in location of the ESD device will be cancelled eachother by adjusting the magnitude and phase of the feedback signal. With thecompensation technique, in normal working conditions of RFIC, the signal of theprotected port is invisible or partially visible to ESD structure, which plays a shieldingeffect, and therefore making large-size ESD device can be used in high frequency range.With improved dual-trench LVTSCR and the proposed co-design method, theperformance of50Ω transmission line with and without the compensation circuit isdiscussed. The results show that the feedback compensation circuit can effectivelyseparate the ESD structure with transmission line in a certain frequency range, thusimproves the matching of the circuit. It can get an appropriate center frequency andbandwidth by adjusting the parameters of the feedback circuit, which does not sacrifice the ESD protection level. With this approach, the application frequency of an ESDprotection is upgraded for several GHz.In summary, based on ordinary analog/digital IC ESD protection technology, theTLP simulation test method for LVTSCR device is improved, and the LVTSCR’scharacteristics in condition of great stress are analyzed, and device structure is improvedto get good switching parameters. A new RF-ESD co-design method based onS-parameters extracting and a feedback compensation measure are proposed, and somemeaningful results are obtained, which provides guidance for the RFIC ESD design.