Research And Design On FFT Pruning In Wireless Communication Systems

As the fast development of the wireless communication technology, its applications are no longer limited to voice and low data rates transmission. The huge market demand from the high data rates communication that can support streaming media, mobile internet, and etc. drives all wireless communication standards in various domains toward higher date rates.But the rapid increase on data rates in wireless communication has also brought a series of challenges to the design and the hardware implementation of wireless communication systems, one important point of which is that on one hand the higher data rates processing and correspondingly the more complex wireless communication systems need more power consumption, but on the other hand the capacity of the battery increases in a much slower rate. Though the semiconductor technology still follows the Moore’s Law, there is still a wide gap between the fast increasing power consumption and the capacity of the battery. More and more attention is paid to improve the design methodology and implementation architecture for higher power efficiency in wireless implementation.Motivated by the importance of power efficiency in wireless communication systems, this dissertation studies the algorithm and the hardware implementation of FFT pruning that can be widely used in wireless communication for higher power efficiency in implementing some special FFT processing, and presents optimization and modification on existing algorithms and implementation schemes with the consideration on algorithm, architecture and hardware implementation.Firstly this dissertation analyzes the application of FFT pruning in wireless communication, such as the DFT-based channel estimation in OFDM systems, modulation and demodulation in OFDMA systems, spectrum sensing in cognitive radio and spectrum shaping in dynamic spectrum access, and ascertain the requirement of FFT pruning in wireless communication. Then the research targets and contents are clarified on the basis of the complete survey on existing related work.Secondly this dissertation presents our studies on generic FFT pruning algorithms. Being aware of the lack of enough flexibility and adaptability in existing algorithms, a novel pruning scheme is developed for mixed-radix and high-radix FFT pruning. The proposed approach is applicable over a wide range of FFT lengths and input/output pruning patterns. In addition, it can effectively employ the benefits of high-radix FFT algorithms that have lower computational complexity.Then this dissertation focuses on the organization of the pruned SFG information which is one of the key points in effectively implementing the generic FFT pruning. The contents in this part concentrate on three aspects:pruned SFG description, storage of the information and the basic method of employing the information in implementing generic FFT pruning. This part also presents a new scheme for cutting down the storage of the pruned SFG information by employing the structural feature of SFG and software-hardware co-design methodology.Following chapter mainly studies the hardware architecture of FFT pruning. Unlike exiting implementation schemes which are pure software on general or specific programmable platform or pure hardware in ASIC, this dissertation designs a reconfigurable IP core with pruned butterfly computing instruction for generic pruned FFT implementation. It adopts a new software-hardware partition strategy according to the algorithm feature of FFT pruning and can be used as the computing engine for FFT pruning. It also provides necessary flexibility for the optimization when implementing FFT pruning algorithm on system level.Finally, based on the reconfigurable IP core, an integrated pruned FFT processor is designed and implemented. The scheme for decreasing storage proposed in previous part is employed for instruction compression and a new butterfly computing order in each stage of FFT processing is adopted that reduce the number of the reading operation on twiddle factor memory and corresponding power consumption. The processor is fabricated in SMIC0.13μm1P8M and the chip testing result validates the design.