Research Of PMT Readout ASICs Over Large Dynamic Range Based On The Shaping And Peak Detection Method

The Large High Altitude Air Shower Observatory (LHAASO) is a multipurpose complex to be built in the 12th Five-Year plan of the National Development and Reform Commission, which aims at discovery of cosmic ray origin and focuses on frontier research fields in high energy physics and astronomy science domain. In LHAASO, the Water Cherenkov Detector Array (WCDA) is one of the key detectors, which consists of more than 3000 Photo Multiplier Tubes (PMTs) scattered under water in an area up to around 80,000 square meters.To achieve wide energy spectrum observation with good energy resolution, the WCDA readout electronics are required to achieve both high precision time and charge measurement over a large dynamic range from 1 to 4000 Photo Electrons (P.E.). The charge resolution is required to be better than 30%@ 1 P.E. and 3%@ 4000 P.E., and the time resolution is required to be better than 0.5 ns RMS in the full dynamic range. To reduce the electronics complexity and hence achieve a good system reliability, ASIC (Application Specific Integrated Circuits)-based design is proposed in this dissertation to integrate all the front-end circuits within ASIC chips, based on shaping and peak detection technique. Two prototype ASICs were designed, to study the techniques of amplification & shaping and Analog-to-Digital (A/D) conversion, respectively. This dissertation is organized as follows.The first chapter introduces the background information regarding LHAASO and WCDA, as well as the front-end electronics scheme based on ASIC design, and outlines the main content of this dissertation.Investigation and research of the time and charge measurement methods in physics experiments are included in the second chapter. Some typical ASICs for PMT readout are also discussed with their structures and performances compared, which form important technical reference for the work in this dissertation.In the third chapter, the system design scheme of ASIC-based front-end readout electronics is proposed according to the features of PMT signal and measurement requirements. The time measurement is achieved by employing leading edge discrimination combined with time-to-digital conversion, while the charge measurement is based on amplification & shaping, A/D conversion, and digital peak detection. Time-to-Digital Converters (TDCs) and peak detection algorithms can be easily implemented based on FPGA (Field Programmable Gate Array) devices, and the work in this dissertation focuses on ASIC design of the key parts-amplification & shaping and A/D conversion circuits, and designed, fabricated two prototype ASICs corresponding to the above two parts, referred as front-end ASIC and ADC ASIC in the following context.The design and simulation of the front-end ASIC is presented in the fourth chapter. Implementation and optimization of the core circuits, such as the input stage, pre-amplifier, shaper, output buffer, and discriminator, are discussed in detail. Simulations were also conducted to estimate the performance of this ASIC.The fifth chapter deliberates on the ADC ASIC. To achieve low power consumption, the Successive Approximation Register (SAR) structure is adopted. The core parts of the ADC ASIC include capacitive digital-to-analog converter (CDAC), dynamic comparator and asynchronous SAR control logic and all of them are optimized based on the trade-off of speed, accuracy and power. The pre-simulation results indicate that the ADC achieves an ENOB better than 10 bit with a sampling rate of 30-40 Msps and the core circuit power consumption is 6.6 mW per channel. In the post-layout simulation, an ENOB of around 9.7 bit is achieved.Test results of both ASICs are presented in the sixth chapter. For the front-end ASIC, the test results show that the time resolution is better than 300 ps RMS and the charge resolution is better than 10%@1 P.E. and 1%@ 4000 RE. As for the ADC ASIC, it functions as expected, and the sampling speed is up to 31.25 MSPS; the ENOB is around 9 bit and 8.6 bit with 2.4 MHz and 15.5 MHz input signal, respectively. As it is the first prototype design in this direction, the above results have targeted our goal at the first stage, and further improvement can be expected based on the research in this dissertation.The final chapter concludes this dissertation, and presents the plan for further research in this direction.