3D Integration Of Carbon-based Electronics System And Synthesis Of Material

Following the Moore’s law, the density of integrated circuits is increasing while the critical dimension of transistor is shrinking continuously. However, due to the limitation of physical size and equipment, the trend of following Moore’s law tends to slow down. Particularly, when the process node of IC is below 10 nm, it will confront the issues such as materials, process and equipment etc. In order to meet the requirement of even high performance, multifunction, miniaturization, low power and cost, on the process level, 3D integration of IC is developed; On the materials level, the carbon-based nanomaterials for instance carbon nanotube and graphene was proposed and regarded as the most potential material candidate for the future electronics. However, when the carbon-based nanomaterials are utilized into the 3D integration of electronics, there are many challenges such as materials synthesis and process compatibility etc. Based on the consideration above, an 3D integrated carbon-based electronics is proposed. With respect to this 3D integrated system, the relevant solution and scenario are illustrated to figure out the challenges when applying the carbon-based nanomaterial into the application of 3D integration.Firstly, based on the cold wall CVD reactor, the synthesis of carbon-based nanomaterial such as HA-SWCNT, MWCNT and graphene was conducted and investigated. During the HA-SWCNT growth in the cold wall reactor, the results have shown that the extra top heater, parallel to the bottom heater, is significant. By using of the extra top heater, on the one hand, the feed gas can be pre-heated; on the other hand, a uniform temperature zone can be maintained. The engineering of catalyst pattern was investigated to achieve the high aspect ratio MWCNT bundles. It has been shown that the hallow hexagonal structure enable the aspect ratio of MWCNT bundles to achieve 10. Additionally, the design of dots pattern is helpful for electrical plating copper on CNT. For the synthesis of bilayer graphene, the nucleation site activity mode is proposed and used to explain the growth. It can be seen that the large coverage of bilayer graphene can be obtained through suitable pre-treatment on copper and controlling of process parameters.Secondly, the post-growth transfer technology is used to figure out the incompatibility between the synthesis process and following process. For the transfer of HA-SWCNT, an PET frame is used to transport the detached PMMA/HA-SWCNT layers conveniently. The tape-assisted method is proposed and developed to transfer the MWCNT bundles into the via, and the yield, highly up to 97%, is achieved when transfer is conducted on the 2-inch wafer. For the bubbling transfer of graphene, a modified PDMS method is utilized to avoid the crack caused by the strong bubbles. In addition, the related characterization of SEM, AFM and Raman was conducted on HA-SWCNT, MWCNT and graphene.Thirdly, for the MWCNT filled TSV interconnect, different polymers are investigated and compared in terms of filling performance. The result has shown the epoxy with natural curing process has the best filling performance. No void and crack is observed after cross-section analysis. Different MWCNT filled TSV such as pure MWCNT, metallic coating MWCNT and CNT/Cu composite have been conducted electrical measurement. The result has shown that CNT/Cu composite by electrical plating process not only has a similar conductivity with Cu, but also a similar CTE with silicon.In the end, by using of the technology and process of material, post-growth transfers and MWCNT filled TSV, the via-last based 3D integration of carbon-based electronics is proposed and developed. Prior to the TSV etching, the graphene transistor is fabricated. After MWCNT filled TSV process, the horizontal metal trace is evaporated to connect the MWCNT filled TSV and graphene transistor electrode. The result has shown that the via-last based 3D integration of carbon-based electronics is feasible and valid.