Low-voltage Oxide Nanowire Electric-double-layer Transistor

In the past ten years, oxide-based nanowire transistors have attracted a lot ofattentions. The traditional nanowire transistors usually require high operation voltages（>10V） because commonly used SiO₂gate dielectrics provide weak capacitivecoupling between the gate electrode and the active channel, due to the dielectricconstant of the commonly used SiO₂is small （3.9）. The high operation is the bigobstacle for the portable nanoscale electronic applications. In order to resolve theabove problems, the electrolyte was used to gate dielectrics，we used the simpletransmission electron microscopy （TEM） nickel grid as a mask instead ofphotolithography, and a mechanical probe was used to transfer nanowires. Thenanofabrication techniques of our nanowire transistors are very simple and theoperation of the device is less than1.5V. And more than the mobility of the nanowiretransistors are very high. So which devices are appropriate for sensors and displayapplications. The main content of this paper is to study the lo w operation nanowiretransistors, which gated by electrolyte with electric-double-layer （EDL） effect. Theobtained several outstanding results are summarized below.（1） The SiO₂were deposited by plasma enhanced chemical vapor deposition（PECVD） technology, which SiO₂solid electrolyte film with large specific EDLcapacitance. At the same time, the proton conductors chitosan film prepared byspin-coated method. The thicknesses of the electrolyte films are all more than2μm, butthat such electrolyte films with a large specific capacitance （>1.0μF/cm²ï¼‰ at20Hzshowed by the C-f test results. The polarization mechanism of the electrolytes wereanalyzed and studied. At the same time, the morphologies of SiO₂solid electrolytewith the different deposition temperature were studied. The EDL effect of theelectrolyte plays an important role in our next work for high performance and novelnanowire transistors investigation.（2） We used the microporous SiO₂solid electrolyte as the gate dielectric for lightSb-SnO2nanowire EDL transistors, which the operation was down to1.0V, and thelow operation mechanism was also studied. The preparation method of our device isvery simple. And the mechanical probe was used to transfer nanowires, which methodcan control the position and the shape of the nanowires. And this method will notpollute the surface of the nanowire. It is very important to prepare high performance nanowire devices. Depositing the ITO source/drain electrodes, we used the simpletransmission electron microscopy （TEM） nickel grid as a mask instead ofphotolithography.（3） In order to further simplify the process of the preparation of nanowiretransistors, we successfully realized the in-plane-gate transistors, which thesource/drain and gate electrodes are in the same plane. So the source/drain and gateelectrodes can be performed using a TEM mask during sputtering of ITO. Thetransparent in-plane-gate Sb-SnO2nanowire transistor shows a good performance withhigh current ratio of105, the subthreshold swing down to92mV/dec and a lowoperation of1.0V. Basing on the good results, a two-serial-capacitor coupling modelhas been proposed to explain the electrostatic gating by us. According to theexperiments and theories indicate that the bottom ITO conducting l ayer on glasssubstrate plays an important role in the in-plane-gate transistor operation. Because theITO conducting layer connects the two EDL capacitors of the gate and channel. Thehigh performance in-plane-gate transistor was prepared by simple method. This hastaken an important step to low-cost mass production.（4） Modulation the threshold voltage of Sb-SnO2nanowire transistor gated bybased on SiO₂solid electrolyte. Two effective methods were used in this paper. Thefirst approach is to change the Sb doping level to control the electrical properties ofSnO2nanowires. The threshold voltages of the Sb-doped SnO2nanowire EDLtransistors shift from0.25V to0.16V when the Sb doping level is increased from0.5%to2%. The second approach is based on the in-plane-gate transistors, noveldouble gate low operation transistors were prepared by using a TEM mask duringsputtering of ITO electrodes. The double gates models are the bottom-plane gates anddouble in-plane gates. According to the results indicated that the threshold of thebottom-plane gates devices were changed from-0.13V to0.73V as the voltage of thein-plane gate is changed1V to-1V. Similarly, the threshold voltage of the dual-planegates mode shifts from-0.35V to0.21V.（5） By the microporous structure of the SiO₂solid electrolyte. A very highspecifc capacitance of8.93μF/cm²at20Hz is measured for the LiCl-treatedmicroporous SiO₂solid electrolyte. The operation voltage of In2O3nanowire transistorgated by the Li-ion-incorporated SiO₂solid electrolytes was reduced to0.4V. Thefeld-effect electron mobility, current on/off ratio, and subthreshold slope of thetransistors are estimated to be739.7cm²/V· s, more than105, and70mV/dec,respectively. （6） Recently, a bioprotonic feld-effect transistor with chitosan nanowire channelwas demonstrated. Here，It is interesting to find that solution-processed chitosan flmswith a large EDL specifc capacitance can also be used as the gate dielectrics forlow-voltage SnO2nanowire transistors. The operation of the device is1.2V. Thefeld-effect electron mobility, current on/off ratio and sub-threshold slope of such ahybrid SnO2nanowire device is estimated to be128cm²/V.s,2.3×10⁴and90mV/dec,respectively.