Investigation Of ESD Reliability For Ultra-Deep Submicron CMOS Devices

Electrostatic Discharge (ESD) induced failure is one of the most important reliability problems of the ICs (integrated circuits), which have become one of the most difficult problems for developing the new generation technology. Under the ultra-deep-submicron technology, the absence of understanding on the ESD damage mechanism limits the transfer of the design experience between generations, which is just the key point of the design of the ESD protecting structure. So this paper investigates the ESD failure mechanism of the MOSFET under the ultra-deep-submicron technology.A mixed-mode simulation platform is built up in this paper which serves as an analysis and design tool for the investigation of ESD protection structure. A TLP(Transmission Line Pulse) measurement system is also set up to get further data for the understanding of the ESD failure mechanism. In this paper, the non-local transport of the NMOSFET under high field is analyzed. The electron energy relaxation time can be regarded as the function of the electron energy due to the characteristic of the non-local transport. Then the empiristic model of the electron energy relaxation time and high field mobility can be got by the Monte Carlo simulation. At last the new parameter models are integrated into the mixed-mode simulation system and the simulation results shows the accordance with the experiment. The critical parameters of the TLP measurement are simulated by the modified simulation model, in which several problems and physical mechanisms are investigated at length.The investigation of short channel silicided NMOSFETs shows that the current crowd is appeared in the silicided diffusion edge. With the help of the recombination in the source region, the new hot spot can be found in the source region, whose temperature can even exceed that in the drain region and cause the thermal breakdown of the MOSFETs. The ballasting resistance of the non-Silicided device can enhance the turning on uniformity, which helps to lead the main current path far away from the channel surface and avoid the early failure. The increase of DCGS(Drain Contact to Gate Space) is a way to increase the ballasting resistance, and may improve the ESD failure threshold. However, when the SCGS(Source Contact to Gate Space) increase, the increase of the source resistance goes against the forward turning on and reduces the uniformity of the segmented BJT, so the benefit of ballasting resistance is restrained. In addition, increasing the channel length can decrease the failure current for the current gain of the parasitic BJT's decreases.The measurement and analysis to the ESD latent damage in 90nm technology are performed under the DC and pulse stress. The results show that when the avalanche hot holes inject into oxide, interface states and neutral electron traps are generated, and then threshold voltage increases and sub-threshold current decreases. The increase of the oxide neutral electron traps can cause the increase of SILC(Stress Induced Leakage Current), the decrease of the breakdown charges and the degeneration of the off-state drain leakage current. The generated interface states during the HE(Hot Electron) stress can shield the injection of the hot holes and lead to lower degradation speed than that of the fresh device. Stress induced oxide damage located not only in the region near the drain, but also in the region near the source. The measurement of the MOSFET under the pulsed TLP stress shows that the longer the pulse duration is, the more the degradation there would be, where the temperature effect is the main reason. It means the longer duration of the TLP stress has, the higher temperature the device may generates, which means the stronger injection mechanism and the more severe damage to the ICs.The ultra-deep-submicron CMOS devices have the shallow junction depth and small size. So the ESD protection structure must turn on quickly to shunt the ESD current. Based on the former investigation, one ESD protection structure is designed using the mixed-mode simulation in the last part of this dissertation. The ESD detected circuit is used to quicken the turn on of the ESD protection structure to avoid the damage of the core circuit. The parameters are adjusted and the validation of the protection structure is verified by the mixed-mode simulation. The test results accord with the design requirement.