SIMD Compiling Optimization For Real-life Multimedia Applications And Multimedia Extensions

Multimedia has becoming a dominating computing field. To meet such a trend, almost all general processor vendors have added multimedia extensions (MME) to their processors. All these MMEs utilized the widely existed SIMD parallelism in multimedia applicaitons. To reduce cost, these MMEs are implemented by reusing existing processor resources (datapath, memory interface, etc.).Currently, programmers are mainly restricted to using assembly to utilize these MMEs. An alternative way is to make compiler automatically generate SIMD instructions from sequential code (SIMD Optimization).SIMD optimization is very similar to traditional automatic vectorization for vector processors. However, not many speedups for real-life multimedia applications have been reported from related researches so far.This dissertation starts by analyzing of both opportunities and obstacles of SIMD optimization from two aspects: MMEs and real-life multimedia applications. We find that we can't take it for granted that SIMD instructions are superior to its scalar counterparts. The strength of MME is at the SIMD support for narrow datatype computing and multimedia typical operations.And the obstacles of SIMD optimization lie in the following aspects:1. MME's key differences from vector processors. It causes vectorization to depend on ISA support and cost evulation.2. Complex code form in source code of multimedia applications.3. The number of multimedia typical operations and its variations. In traditional vectorization, idiom is recognized by 1:1 recognition module for each operation. However, due to the number of multimedia typical operations and its variations, this method is unpractical now. On one hand, the number of modules will be greatly increased, leading to the writing and porting of compiler very hard. On the other hand, we can't enumerate all the possibilities. The effect of recognition may not be good, either.Then, we extends traditional dependence-based vectorization algorithm by adding two new stages: code normalization and vectorizable operation recognition.