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Basic Research On NoC

Posted on:2006-03-29Degree:DoctorType:Dissertation
Country:ChinaCandidate:G M ZhouFull Text:PDF
GTID:1118360152990182Subject:Precision instruments and machinery
Abstract/Summary:PDF Full Text Request
During the 1990s more and more processor cores and large reusable components have been integrated on a single silicon die, which has become known under the label System on Chip (SoC). Main difficulties of this era were, and still are, the standardization of the component interfaces and the validation of the entire system with respect to its physical and functional properties. Buses and point to point connections were the main means to connect the components. Buses are attractive because they provide high performance interconnections while they can still be shared by several communication partners. Hence they can be used very cost efficiently.As silicon technology advances further, several problems related to buses have appeared. Buses can efficiently connect 3-10 communication partners but they do not scale to higher numbers. Even worse, they behave very unpredictably as seen from an individual component, because many other components also use them. A second problem comes from the physics of deep submicron technology. Long, global wires and buses become undesirable due to their low and unpredictable performance, high power consumption and noise phenomenon. A third problem comes from the application perspective. Designing and verifying the inter-task communication in a system is a hard problem per se. Getting it to work and dimensioning communication resources correctly is even harder for large bus based communication networks due to the unpredictability of the communication performance. Moreover, every system has a different communication structure, making reuse difficult.As a consequence, around 1999 several research groups have started to investigate systematic approaches to the design of the communication part of SoCs. It soon turned out that the problem has to be addressed at all levels from the physical to the architectural to the operating system and application level. Hence, the term Network on Chip (NoC) is today used mostly in a very broad meaning, encompassing the hardware communication services and a design methodology and tools to map applications onto a NoC. All this together can be called a NoC platform.NoC research is still in its infancy and no real SoC has been built using NoC. However, it is expected that future generations of products will have NoC based components. There is reason to believe that the emerging NoC paradigm promises to address the address these trends and challenges and is a likely basisfor future System on Chip platforms and methodologies.The NoC area has grown dramatically as a research topic over the last few years. Today, probably over 30 groups at Universities, research institutes, and industry are active in this area. But no one is active in NoC area in China. This dissertation first introduces the concept of network on chip, and studies the NoC methodology in a systematic manner. After having presented a thorough study, this dissertation proposes a new design method, and studies the network assignment algorithms include mapping algorithm and routing path allocation algorithm. The main work and achievements are as follows:1. A kind of NoC design method based on communication is proposed in this dissertation, which makes NoC achieve better performance by coordinating network communication of NoC. And author further discuss the key technologies among them in detail.2. A kind of hybrid ant colony optimization algorithm is proposed in this dissertation, which realizes the mapping applications onto a NoC as well as achieves lower power consumption.3. Based on the thorough analysis on the network communication of NoC and study the shortest path algorithms, a directed Ford-Fulkerson algorithm is proposed in this dissertation. After having mapped the processing elements onto a NoC, it optimizes the overall executing times of the actual application by performing routing path allocation based on the network traffic on NoC.4. The standardization of the resource network interface is the key technology. According to SoC design experience, a unified interfac...
Keywords/Search Tags:Network on Chip, map, path allocation, communication, ant colony optimization algorithm, shortest path algorithm, resource network interface, PCI bus, IP reuse
PDF Full Text Request
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