Studies Of High K Dielectric Materials On Bulk Si And SOI And Their Applications

Silicon-on-insulator (SOI) and high dielectric materials are two of the cutting-edge research focuses in microelectronics industry. Based on the demands and supports of special Funds for Major State Basic Research projects and the National Natural Science Foundation of China, we have made a series of investigations on fabrication and characterization of high K dielectric materials on bulk Si and SOI substrates, as well as the applications of the materials. Main new results are drawn as follows:Amorphous and uniform ZrO2 thin films were fabricated on Si substrates by ultrahigh vacuum electron beam evaporation. The thin films have good thermal stability. When the annealing temperature was kept under 600, the films kept amorphous and the interfaces between ZrO2 and Si substrate were clear and sharp. No interfacial products were probed. But when the temperature increased to higher than 700, the amorphous thin films changed into mixture of amorphous and polycrystalline ZrO2. Also interfacial products appeared.ZrO2 thin films were deposited by pulsed laser deposition. We found that substrate temperature had a great influence on their surface morphology, surface roughness and characteristics. But the ZrO2 target used to deposit ZrO2 thin filmswas fabricated by high temperature sinter, so the target was in its polycrystalline state. So the films prepared by this technique tended to crystallize at low temperature.It is the first time that amorphous ZrO2 thin films were fabricated on ultrathin SOI substrates by ultrahigh vacuum electron beam evaporation. The thermal stability between ZrO2 thin films and top silicon layer of SOI substrates were studied. Similar phenomena were observed as compared to the films on bulk Si substrates. The amorphous thin films could keep stable after annealed in O2 ambient ranged from500 to 700 . But when the annealing temperature attained 700 , an interfacial product was observed between ZrO2 thin films and top silicon layer ofSOI substrates, which was deduced to be ZrSixOy. This layer of interfacial oxide was confirmed to be beneficial to reduce the interface state density.It is the first time that we fabricated ZrO2/Al2O3 and Al2O3/ZrO2/Al2O3 high nanolaminate gate stacks on ultrathin SOI substrates by ultrahigh vacuum electron beam evaporation. The high frequency capacitance-voltage (C-V) characteristics of SOI MOS capacitor with the gate stack were systematically studied. It is the minority carriers that determine the high frequency C-V properties of the fully depleted SOI MOS capacitor, opposite to the case of bulk MOS capacitors. The gate capacitance in the inversion region decreased with the increase of gate biases due to the inherent high series resistance of our SOI MOS capacitor. While the gate capacitance in accumulation region became higher with the increase of ac frequency. The reason is that the series resistance becomes more significant because of the lower impedance of the capacitor at higher frequency.The two-dimensional device simulation software Medici was used to simulate the behaviors of MOS and SOI MOS devices with ZrO2 gate dielectrics, which was compared with those of traditional MOS and SOI MOS devices. And the simulation results are very important, for they could provide systematic guidance for applications of high K gate dielectrics into devices.Fabrication of SOI based two-dimensional photonic crystal waveguide was designed and patented. Initial theoretical calculations were performed on the photonic crystal waveguide. It is found that there are two-dimensional photonic bandgaps in the SOI based photonic crystal waveguide with triangular lattice. H+, He co-implantation and Smart-Cut technology were employed. The fabrication process and the detail parameters were created.