| Resistance random access memory (RRAM) is an intriguing approach for next generation non-volatile storage, owing to its attractive combination of density and speed. However, the microscopic physical mechanism of RRAM has been controversial, which became a major obstacle to potential applications. In this dissertation, the RRAM memory cells based on peroskite oxide SrTiO3(STO) are prepared. By means of changing the metal electrode and the introduction of a dielectric layer, the resistance switching characteristics are investigated, and the new principle of logic devices is developed. The main results are as follows:1. Study on Au/STO/Ti memory cellsThe Au/STO/Ti memory cells are prepared. The electrical measurements show that the contact on STO/Ti interface is ohmic, while the contact on the Au/STO interface is Schottky. In the range of±2.5V, the memory showes a bipolar resistance switching with counter clockwise polarity. The analyses on I-V and C-V data show that the resistance change is due to the change in Schottky barrier height and/or width by trapping/detrapping effects at Au/STO interface defect states. Netative bias applied to memory can induce a bipolar resistance switching with clockwise polarity which comes from redox reactions induced by the migration of oxygen vacancies. These two bipolar swithing with opposite polarity is due to the different distribution of defect states in STO films.2. Study on Au/STO/Pt memory cells and its application in new principle devices(I) The metal/oxide interface has crucial effect on the switching properties of memory cells. Pt as bottom electrodes and the electrical characteristics of Au/STO/Pt are investigated. XPS analysis shows that the valence states of contained elements in STO films are Sr2+, Ti4+, O2-,and there exists a certain amount of oxygen vacancies. The initial state of the Au/STO/Pt cell show rectifying characteristics due to Schottky contact between Au and n-STO. The memory, applied a large reverse bias (about-6～-8V) with1mA compliance current (CC), showes bipolar switching behavior. However, if the CC is set to10mA, the memory will show unipolar switching behavior. Both types of switching with different polarity are interchangeable. The polarity dependence of the CC is due to different current in forming process resulting in the formation of different defect density. Bipolar resistance switching is due to the change in Schottky barrier height and/or width by trapping/detrapping effects at Au/STO interface defect states, and unipolar switching is due to the formation and rupture of conductive filament. The non-volatile properties show that the resistance state in unipolar switching has continued for two weeks without significant change, while the resistance state in bipolar switching would be changed after a few hours.(2) The study on IMP logic is still in an initial stage, and there is no report about IMP logic enabled by unipolar memristors. In this work, the IMP logic circuit is formed by Au/STO/Pt unipolar switch memory. By means of the combination of theoretical simulation and experiment, it is explored that the electric parameters of voltage and current to obtain IMP logic and the stability of the device. This unipolar memristors have a large switching ratio (>1000), linear I-V relationship in low resistance state, and modulation factor of1.2showing that the weak depolarization of switch. These rusults prove that the reliability of IMP is effectively enhanced. However, there is a large variation in set and reset threshold voltage for the Au/STO/Pt unipolar switching device, which could impact the reproducibility of IMP results. The calculation indicates that the influence of the threshold voltage instability on the IMP operation can be lessened by selecting the appropriate value of RG in series. To thoroughly solve this problem, the set and reset threshold voltage should be stabilized through the optimization of unipolar switching materials and the design of memristor structures.3. Study on Au/NiO/STO/Pt memory cellsThe interface barrier plays an important role in resistance switching, so p-NiO/n-STO heterojunction prepared by PLD technique. and resistance switching characteristics of the Au/NiO/STO/Pt memory are investigated in detail. The main results are follows:(1) When a lower CC is set during the electrical test, the memory presents bipolar resistance switching due to the presence of the interface barrier, which can reversiblly convert between clockwise and counter clockwise. The bipolar resistance switching with clockwise (counter clockwise) is due to a change in interface barrier height and/or width by trapping/detrapping effects at NiO/STO (STO/Pt) interface defect states.(2) When a higher CC (10mA) is set during the electrical test, the memory shows unipolar resistance switching due to the disappearance of the interface barrier. The unipolar switching can be repeatedly switched in the negative bias, while in positive bias the switching disappear after only about4-7cycles. The reason is the different bias polarity driving oxygen vacancies in opposite direction, so the location of switch moves up and down with the bias. Under negative bias, conductive filaments consisted of defects rupture and form in STO films. While under positive bias the rupture position of conductive filaments move to the NiO/STO interface, and the Ni conductive filaments in NiO films is oxidized by O2-, which results in the disappearance of switch.
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