A Study Of Multicore-Based Virtualization Technique

Nowadays, with development of computer hardware compared to the slower software computing, the requirement of huge information resources management and service consolidation, virtualization technique, as one solution, has been deemed as one of the research points prompted by cloud computing. Based on software and hardware technique, virtualization technique assigns fundamental resources to several or only one execution environments to satisfy its requirements. Currently, virtualization technique has been widely applied on many important research domains, such as service consolidation, kernel developing, kernel debugging, security computing, parallel computing between OSes and system migration, etc. To improve system performance with soft virtualization technique, Intel and AMD propose hardware-assisted virtualization that prompts virtualization technique.Multicore gives virtualization technique a chance. With chip multiprocessors, the execution of virtualization is easier than before, since different processes are assigned to each core. In addition, with the help of virtualization, each core can execution several virtual machines, rather than only one. Indeed, the advantages of multicore-based virtualization technique, such as cluster computing, dynamically assigning resource, efficiently utilizing system resources, etc, has been confirmed by many companies and general-purpose guests, because it utilizes a fewer hardware to help people finish works and gets better performance.Combined with multicore technique, virtualization technique can be improved further. According that mentioned, in this paper, the research is depicted in detain as follow: 1. This paper proposes qualitative analysis and quantitative analysis of dynamic binary translation (DBT) system's performance. According analysis results, we change translation part, execution part and optimization part into various threads assisted by multicore. Then this paper presents dynamic code cache (DCC) policy based on working set. Compared to previous works, this policy fits program's behaviors and reflects program's locality feature.2. This paper proposes multithreaded DBT system---MTCrossBit, where translation/execution thread and optimization thread are executed concurrently. In this architecture, optimization thread used to build superblock is employed, and this is to efficiently utilize multicore resource to improve system performance. To address communication issue between threads, a novel lock-free communication mechanism--- Assembly Language Level Communication (ASLC), is presented, which can fully avoid lock/unlock algorithm. Another key point is that private code cache for each thread is presented in this architecture, which avoids polluting code cache between various threads.3. This paper proposes multithreaded DBT system---MTEE CrossBit, where translation/optimization thread and execution thread are executed concurrently. In this architecture, to efficiently execute target code block, several translation threads (including optimization part) are executed concurrently to translate basic blocks and superblocks. And this leads no context switch between translation thread and execution thread compared to original CrossBit. Then this paper also presents another key technique----BranchTree utilized to manage translation threads and execution thread.4. This paper presents two software tuning methods for KVM-based embedded virtualization system. In this architecture, to minimize the effect for RT guest caused by GP guest, this paper presents prioritization policy, which enhance the priority of RT guest to occupy CPU resource as long as possible. So the GP guest cannot frequently influence on RT guest. Then this paper proposes CPU shielding, which prevents the RT guest from being adversely affected by harmful workloads, like interrupt-off regions and cache pollution, thus achieving the best real-time performance.5. This paper presents two cache-based tuning methods for KVM-based embedded virtualization system, Page table prefetch (PTP) and cache partitioning (CAP) assisted by prefetch technique and page coloring. In previous works, various cache partitioning solutions were executed in simulation, while in this paper it is applied on physical cache. Compared to previous works, the goal in this paper focuses on not only better real-time response but also high system performance.