Study On The Multiple-plane And Multiple-stage Packet Switching Technology

With the evolution towards high-speed transportation as well as access network, the scalability of network routers is challenged rigorously. The novel multiple plane and multiple stage (MPMS) packet switching technology can integrate multiple small-scale switching units into a large switching network, which is able to break the bottleneck of single switching fabric and increase the scalability of network routers. Therefore, the MPMS switching technology is causing more and more attention from academic and industry domains. The MPMS switching technology, however, is only at its initial research phase for lacking of theoretic basis and mathematics models. Many important technical issues of MPMS have not been studied deeply, which holds back its application in practical network routers seriously.Combined with the research work of the National Basic Research Program of China (973 program) of"the integrated network architecture model and the switching and routing theory and technology", regarding to the scalability requirement of router switching fabric, a universe architecture and mathematics model of the MPMS are proposed, and the analysis methods and performance evaluation techniques are built up, which are based the functional units and linking structure. Two novel MPMS switching system with different buffering methods are proposed and studied evaluated. To meet the bandwidth sensitive services in Internet, a bandwidth guaranteed scheduling technique is proposed. The main research work of this paper includes:1. The universal architecture and the directed graph model (DGM) are proposed. The universal architecture and organization method are proposed and analyzed based on the functional unit subsets and linking connection subsets. With the directed graph theory, the DGM model of the MPMS switching system is proposed, and the characters including neighboring relations and port reachability are defined, and the model graph is also provided. Based on the defined model character, the vertex competing and balancing property and the switching path are defined. The performance expansive ratio is defined to describe the scalability accurately.2. A novel input/output buffered Clos-type MPMS (MSMC&MPMS) packet switching system is studied, and its topological structure is proposed, and then its DGM model is built up. The topological characters, including graph complexity, neighboring connectivity, and port reachability, are studied, and then the topological measure graph is given of the MSMC&MPMS system. It is shown that, demultiplexors and input switching units belong to balancing vertex, while middle switching units, output switching units and multiplexors belong to competing vertex in the MSMC&MPMS system. The switching path count between any demultiplexor and multiplexor pair is equal to P×m, where P is the switching plane number and m is the middle switching unit number. The number of switching ports can be expanded to PN times, where PN refers to the maximum port count of single switching fabric, and the rate of switching ports to P times, and the switching capacity to P×PN times, while the fabric structure is only linearly increased with the switching plane numbers.3. A novel central stage buffered Clos-type MPMS (CBC&MPMS) packet switching system is studied. Its topological structure is proposed, and then its DGM model is built up. The topological characters, including graph complexity, neighboring connectivity, and port reachability, are studied, and then the topological measure graph is given of the CBC&MPMS system. Demultiplexors, input switching units and middle switching units I belong to balancing vertex, while middle switching units II, output switching units and multiplexors belong to competing vertex. The switching path count between any demultiplexor and multiplexor is P×m×k, k times the MSMC&MPMS system. It has the same expansive parameters with that of MSMC&MPMS, but its fabric complexity is 33.3% higher than that of MSMC&MPMS.4. MSMC&MPMS is proved to be fabric non-blocking under condition of P×m×k≥N or P×m≥n, where k is input/output switching unit count, N is system port count and n is input/ output switching port count, while CBC&MPMS is fabric non-blocking with parameters satisfying P×m×k2≥N or P×k×m≥n, needing much less input/output switching units. Meanwhile, MSMC&MPMS is proved to emulate an OQ switch with speedup factor satisfying S≥2/P or S≥N/(P×m×k), while CBC&MPMS can emulate an OQ switch if S≥1/P and m≥N/(P×k), whose TSP is only 1/2P times that of MSMC&MPMS.5. A novel bandwidth guaranteed scheduling technique of the MPMS switching system is provided. The scheduling model of demultiplexors, multiplexors and input/output /middle switching units are provided, and a bandwidth guaranteed concurrent round-robin dispatching algorithm (called BG-CRRD) is also designed. Simulation results show that, the algorithm can achieve 100% throughput under Bernoulli uniform traffic, and the optimal delay can be achieved when the switching plane count is three. Under nonuniform traffic, it can gain a throughput much higher than CRRD, and can achive a throghput of 92% under worst case, which is 29% higher than that of the CRRD algorithm. Under overloaded traffic, it can allocate output-link bandwidth among Cell flows according to their reserved bandwidth, and therefore can satisfy the bandwidth requirement of service folw and share bandwidth fairly. So the BG-CRRD scheduling algorithm can satisfy the scheduling demands of different bandwidth sensitive services.