Study On Intelligent Analog Circuit Fault Diagnosis Method Based On Lifting Wavelet Analysis And Optimized SVMs

Analog circuit testing and fault diagnosis play key roles in many fields such as circuit design, equipment manufacture and instrument maintenance. Currently, the study on the two aspects is still a challenging topic for academic researchers and engineers in electronic testing area. As the electronic technology develops rapidly, complexity and integration scale on analog circuits are increased simultaneously. More strict requirements for running reliability are desired also. It is difficult for traditional fault diagnosis theories and methods to solve the problems of fault diversity and complicacy, which are caused by continuous response, nonlinearity, and tolerance on component parameters due to the characteristics of circuits. Intensive study on intelligent fault diagnosis theories and methods with practicality and high performance is an urgent task. The fault feature extraction and effective fault identification methods are two critical parts for intelligent fault diagnosis. The optimization of feature extraction and design for classifiers for analog circuit fault diagnosis system are discussed deeply in this dissertation, based on modern testing technology with combination of wavelet analysis and support vector machine (SVM), which typically represent intelligent computing techniques. The main research contents and achievements are summarized as following:Wavelet analysis based analog circuit fault detecting sensitivity and feature extraction optimization method are studied. Good localization on time-frequency domain of wavelet transformation provides better feature representation for faulty circuits than unitary time or frequency domain analysis. However, different wavelets present diverse resolution for fault recognition. Root mean square (RMS) score is proposed for measuring fault detecting sensitivity of wavelets for analog circuits in this paper. According to separating distance for classification, a measure criterion is presented for optimal wavelet basis selection, which leads to acquire better fault feature extraction. The experimental results show that this method can effectively improve fault identification accuracy.Optimized analog circuit fault diagnosis approach based on wavelet neural network is researched. Aiming at the fact that conventional BP neural network usually converge to local minimum in fault diagnosis, wavelet analysis and neural network are combined to construct wavelet neural network (WNN) frame for fault diagnosis. WNN achieves high convergence speed and low fault diagnosis error rate due to the multi-resolution property of wavelet function with adaptive learning algorithm. To avoid the network gegenerality degradation caused by training convergence direction deviating from globally optimal point for structure redundance, genetic algorithm is used to optimize the structure and parameters of the network. Optimal WNN is obtained with simplified structure and higher fault diagnosis efficiency.Lifting wavelet transform and support vector machines based analog circuit fault diagnosis method is studied thirdly. As WNN structure and pattern complexity greatly impact the results of fault classification and diagnosis under condition of large number of fault categories, support vector machine (SVM) algorithm is proposed to fault diagnosis. SVMs outperform neural network in many ways such as learning ability for small number of patterns, tackling nonlinearity and high dimension pattern recognition. It shows less time-consumption for computing in the same instance. Simultaneously, lifting wavelet analysis method, which is independent of Fourier analysis and easy to implement integral wavelet analysis, is applied to fault feature extraction of analog circuits for precise expression of faulty information. Lifting wavelet transform (LWT) presents better fault feature quality with higher partition characteristic. The presented LWT-SVM fault diagnosis approach acquires higher performance on diagnosis veracity and efficiency than neural network.Optimized binary tree decision SVM (DBT-SVM) based hierarchical fault diagnosis methods for analog circuits are researched. SVMs are proved as an effective approach for fault diagnosis. When SVMs are used for multi-fault diagnosis in analog circuits, the diagnosis accuracy and efficiency largely depend on the extension strategies for multi-classification. On condition that there are large numbers of fault categories and high similarity even overlapping among various fault classes occur, conventional SVM combination strategies for fault diagnosis cannot get good results on fault recognition accuracy and efficiency due to not considering the clustering properties of fault features. DBT-SVM is able to decrease inseparable area to gain classification performance improvement, but it need structure optimization. This paper studies two ways for optimized DBT-SVM methods: minimum spanning trees SVM and fuzzy clustering optimized DBT-SVM (FDBT-SVM) with wavelet fault feature fusion. According to the separability measure of fault classes, multi-classification DBT-SVMs with large margins are constituted to avoid the inseparable fault area. The presented methods largely enhance fault diagnosis accuracy and efficiency comparing with conventional multi-classification SVM algorithms.