Fundamental Research On Methods Of Inducing Stain Into Silicon And Related MOS Devices

As the device feature size scaling down, the Si-based integrated circuits close to the physical limits that brings great challenges and technology crisis to Moore's law. Fortunately, the Strained Silicon Technology, by which adjusting the silicon band structure to enhance the device performance, becomes one of the most effective and attractive methods that keeps the Moore's law in silicon latter era. So, this thesis focus on researches of the relationship between strain and stress, methods of introducing strain into silicon, the mechanics of mobility enhancement with strain in MOS device and the growth of strained silicon material.Firstly, based on elastic theory, the relationship between strain and stress in silicon with corresponding reciprocal space vary are derived and presented under uniaxial and biaxial stress respectively, which builds the foundation for calculating the effect of strain on energy band according to linear deformation potential theory and provides theory reference of stain induction methods and analyzing the testing results. In the light of that, taking advantage of X-ray diffraction theory, two testing methods of characterization of the tiny strain and local strain induced in Silicon are developed by using High-resolution X-ray diffraction, HRXRD.Secondly, the band structure of Si is calculated by First Principle theory under the uniaxial and biaxial stress, respectively, and the effective mass of carriers is calculated by curvature. The mechanism of strained Si carrier mobility enhancement is obtained by analyzing the change of effective mass and scattering probability of carriers under strain, which provides a theoretical reference for strained Si devices design. At the same time, the splitting value of the conduction band and the valence band of silicon under uniaxial and biaxial stress are derived, in the light of the linear deformation theory, and the relationship between electron mobilityμn and strain degreeε// is presented.Thirdly, the mechanism of local strain induced into silicon by SiN cap and shallow trench isolation STI are theoretically studied. The experimental results measured by characterization methods presented above show that the intrinsic stress of SiN cap is the main factor when thickness of film is thin, that slows down with increasing to the critical thickness and eventually reaches saturation. And the strain induced by STI is sensitive to layout geometry. Furthermore, an effective strain memory method with size-free is proposed based on the experimental results and the relationship between stain and stress in silicon. By setting Si buffer and poly-Si side wall, high quality local biaxial compressive strain Sio.8Geo.2 meterial with surface roughness of 0.45nm and lower density of defect(<103cm-2) is successfully fabricated, that pesents a method of inducing local biaxial compressive strain for applying in PMOS.Finally, the mechanism of low temperature silicon LT-Si making the pseudomorphic SiGe relaxed below the critical thickness and reduction of dislocation density in epitaxy layer is presented based on screw dislocation formation and slip model. In the light of experimental results, strained-Si material with ultrathin relaxed Si1-xGex virtual substrate could be grown by smartly combining LT-Si technique and ion implantation. And a strained Si PMOSFET is fabricated by the material and the hole mobility of it increases by about 30% compared to bulk Si PMOSFET with same processing.In conclusion, the effective strain memory method based on energy band theory of strain enhancing carrier mobility of silicon and elastical stain-stress relationship could induce defferent type of stain into Si CMOS device, which provides a way to realize strain engineering without layout size limitation.Meanwhile, smartly combining the LT-Si technology and ion implantation, biaxial tensile strained silicon material with ultrathin relaxed Si1-xGex virtual substrate can be used to fabricate NMOS. The local biaxial compressive strain Si1-xGex material fabricated by the method can be used to fabricate PMOS. This gives another way to induce strain engineering into Si CMOS.