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Research On Hierarchical Performance Analysis Methodology Of NP-based System

Posted on:2008-06-12Degree:DoctorType:Dissertation
Country:ChinaCandidate:Z DanFull Text:PDF
GTID:1118330332478535Subject:Computer software and theory
Abstract/Summary:PDF Full Text Request
From the birth of network processors (NP), they gain lots of attentions from many companies and researchers, because of their high performance, programmable, extendable and fast to markets characteristics. More than 30 companies have brought out more than 500 products or designs. Cisco, ALCATE, Deceng, HuaWei 3Com etc. have built routers, switches and security devices using these processors.But now, the development of network processors technology doesn't match people's wish. Especially when building a system with NPs, we have to face the fact that the absence of a performance analysis methodology, which can help us evaluate the various designs among different hardware and software architectures, design and optimize NP-based systems.The main purpose of this dissertation is to solve above problems by the study of performance analysis of NP-based systems. And the dissertation makes the following contributions:1. The dissertation presents the extended general network processors topology (EGNPT) and level based NP software depiction, which solve the problem of how to depict the different NPs'software and hardware architectures in universal form. The dissertation also realizes the mapping of the NPs'software architecture to multilevel parallelism. This work builds the base for the performance analysis of the NP-based applications with different software and hardware architectures.2. The dissertation brings out "compute budget" and "times of memory accessing" restrictions when the software being mapped to hardware. These restrictions reduce the number of mapping set's (design space) elements and the complexity of the searching working. The constricting test of IPv4 Forward design space shows the original size is 8947848 times of the reduced size. This work makes the propriety objects for NP-based systems performance analyzing.3. The dissertation presents a hierarchical performance analysis methodology for network processor applications, which overcomes the difficulties brought by NP's multilevel parallelism characteristic. The test results show that the error of this methodology is less than 8% and other performance analysis methods, whose errors are 10%-17%. The practice of the methodology in "IPv4 Forward", "NP-based Network Testing Platform" and "NP-based Network Inspecting System" shows that it can provide technology supports and references for the NP-based system's performance evaluating, designing and optimizing.4. On the application/function level, the dissertation presents a line based analysis methodology to solve the multithreads program performance evaluation. The test results of IPv4 Forward show that the error of this methodology is 0.47%. This work provides highly accurate parameters for the performance model on system/platform level.5. On the system/platform level, the dissertation models the system using a GI/G/m/∞/FCFS queueing network, which solves the performance analysis of multiclass inputs and multiserver node open queueing network. The model depicts the system more closely to the real world than other models, which use one class customer, Poisson arrival process and Exponential serve time distribution queueing network to model the system.6. The dissertation uses decomposition to solve the GI/G/m/∞/FCFS muliclass open queueing network, and gives a new formula for the coefficient of variation of the interdeparture times. Based on this method, the dissertation designs a queueing network based packet random sending algorithm and implements it in the "NP-based Network Test Platform".The dissertation make efforts in NP software and hardware depictions and mapping relations, NP's multilevel parallel program performance analysis and queueing networks based performance model. Further researches will be needed, including:a. more testing and evaluating of difference applications on various hardware platforms to validate the universality of the dissertation's methodology.b. further studies of NP's instructions parallelism and more analysis of program/data relativity.c. building performance analyzing software tools with the methodology of this dissertation.
Keywords/Search Tags:Network Processor, Performance Analysis, Multilevel Parallelism, Non-Product-Form, Queueing Networks
PDF Full Text Request
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