| Router is a networking device that forwards data packets between computer networks. It has been playing a fundamental role ever since the birth of the Internet. However, as the Internet is developing rapidly, the design of traditional routers gradually becomes outdated that cannot meet with the growing demand from either Internet Service Providers(ISPs) or end-host users. On one hand, in order to maintain the link connectivity, traditional routers have to keep 24/7 standby, consuming a huge amount of power.Therefore, a router supporting power conservation will be of great value for ISPs to reduce the energy budget. On the other hand, traditional routers are designed strictly following the “end-to-end principle†that forward packets without distinction. They can hardly provide fine-grained, application-aware QoS support for end-host users. Therefore, a router supporting application-aware traffic differentiation will be warmly welcomed by end-host users. In this paper, to satisfy the growing demand from both the ISPs and the end-host users, we redesign router’s line cards to enable power conservation and application awareness. The main contributions of this paper are listed as follows:1. Redesign of router’s line cards to support fast wakeup from the sleep mode is proposed. Many schemes are proposed to improve power efficiency of routers by putting links to sleep when idle and waking them up when needed. A presumption in these schemes, though, is that router’s line cards can be waken up in zero time. However,through systematic measurement of a major vendor’s high-end router, we find that it takes five minutes or even more to get a line card ready under current implementation. In order to apply these power-saving schemes “seamlessly†to existing routers, we propose several designs to reduce the line card wakeup time. Especially, a slim slot of popular routing prefixes are downloaded with higher priority, so that the line card will be ready for forwarding most of the traffic much earlier. We apply dynamic programming to ensure fast and correct longest prefix match lookup during prioritized routing prefix download.Experiments on real hardware show that the line card wakeup time can be reduced from40.8s to 127.27 ms.2. Design and implementation of an FPGA-based application-layer protocol identification system to assist the application-aware traffic differentiation on high-speed routers are proposed. Unlike the software-based approaches built on multi-core processors, we build the entire system via FPGA to satisfy the performance requirements of backbone networks. By exploiting the temporal locality of the transport-layer traffic, we design a hierarchical memory architecture. By exploiting the burst access feature of DRAM, we propose a hash table with fixed-sized buckets as the flow table data structure. We propose lazy timeout mechanism to reduce the memory bandwidth consumed by the flow timeout operation. We also craft device-independent layer to hide the low-level hardware details and implement that abstraction layer via a 3-stage command pipeline. Experiments show that our system can reach 70 Mpps throughput, ready to serve OC-768 backbone links.3. A novel flow table data structure dedicated to cost-effectively maintaining 100 M concurrent flows is designed. Effectively resolving hash collisions is the key to improving flow table performance. Multiple choice hashing is proposed in previous works to effectively reduce the hash collision resolution time but at the cost of huge on-chip memory usage. To reduce the on-chip memory cost, we propose bandwidth-greedy hashing by exploiting the burst access feature of DRAM and allocating the on-chip memory on demand for only a few hash table entires without compromising too much system throughput.Evaluations show that with off-the-shelf DRAM, only one DRAM burst access is needed in our scheme for flow state lookup, with minuscule on-chip memory cost of less than16 MB to summarize 100 M concurrent flows at a throughput of 122.82 Mpps.
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