Keyword [Phase Detector] Result: 41 - 60 | Page: 3 of 4 41.  Design Of PLL Frequency Multiplier Applied In 3.125 Gb/s SerDes Transmitting System 42.  The Research Of Divider Used In Harmonic Rejection System And Phase Error Detection 43.  Design Of CPPLL Applied In High Speed Circuit 44.  Research On Phase Difference Detection In Magnetic Induction Tomography 45.  Miniature And Low Phase Noise Sampling Phase-locked SIW Oscillator 46.  Design Of A Clock And Data Recovery Circuit Based On A Delay-and Phase-Locked Loop 47.  Design Of Delay Locked Loop Based On Active Delay Cell 48.  Research And Implementation Of A New Digital Phase-locked Technology 49.  Design Of High Speed PFD,CP And ILFD In Mm-Wave PLL 50.  An Adaptive Random-valued Impulse Noise Removal Algorithm Using A Two-phase Detector 51.  Clock and data recovery circuits for 10 giga-bit-per-second broadband receivers in 0.18mum CMOS 52.  10-Gb/s CMOS clock recovery circuit building blocks using dual-substrate technique 53.  Design and modeling of high-speed clock and data recovery circuits 54.  Clock multiplier unit and clock data recovery circuit for 10Gb/s broadband communication in 0.18mum CMOS 55.  A multi-gigabit CMOS transceiver with 2x oversampling linear phase detector 56.  Gallium-arsenide Monolithic Microwave frequency halver and phase detector for use in a phase locked oscillator 57.  Design Of Clock And Data Recovery Circuit For 40Gb/s Serdes 58.  Research And Design Of Low Jitter And High Speed Clock And Data Recovery Circuit 59.  A CPPLL Design Based On Relaxation Oscillato 60.  Research And Design Of Key Technology Of Silicon-based CMOS Phase Locked Loop   <<First  <Prev  Next>  Last>>  Jump to

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