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Keyword [submicron]
Result: 161 - 180 | Page: 9 of 10
161. Physical modeling and characterization of submicron SOI and bulk MOSFET devices
162. Design-for-testability techniques for deep submicron technology
163. Valence-band electron tunneling in deep-submicron metal oxide semiconductor field-effect transistors
164. Poly-silicon-germanium gate technology and direct-tunneling oxide for deep-submicron CMOS application
165. Signal integrity and low power issues in deep submicron VLSI design
166. Integration of ultrathin (1.6 -- 2.0 nm) RPECVD stacked oxide/oxynitride gate dielectrics into dual poly-Si gate submicron CMOSFETs
167. Physical modeling and analysis of deep-submicron silicon-on-insulator CMOS devices and circuits
168. Collinear acousto-optical interaction in proton-exchanged lithium niobate, and Submicron silicon-on-insulator metal-oxide-semiconductor field-effect-transistors
169. The design, fabrication and characterization of non-elevated and elevated source/drain p-channel MOSFETs for deep submicron technologie
170. Scaling of buried-channel MOSFETs for submicron applications
171. Advanced transport models development for deep submicron low power CMOS device design
172. High speed submicron CMOS oscillators and PLL clock generators
173. A deep submicron drain-current and charge model for MOS transistors
174. Development of submicron CMOS in 6H-SiC
175. A comprehensive model of submicron chalcogenide switching devices
176. Integrating selective silicon epitaxy with thin sidewall spacers for submicron elevated source/drain MOSFETs
177. Computer visualisation and proximity effect correction for submicron electron beam lithograph
178. UT-MiniMos: A hierarchical transport model based simulator for deep submicron silicon devices
179. High microwave power submicron gate transistors on indium phosphide
180. Modeling and simulation of the fully depleted silicon-on-insulator MOSFET for submicron CMOS IC design
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