Font Size:
a
A
A
Keyword [floorplan]
Result: 21 - 40 | Page: 2 of 3
21.
Research Of Topology Generation Algorithm For Application Specific Network-on-Chip
22.
Multi-power Supply Network Design For SoCs
23.
Floorplan And Power/Ground Network Co-design Technique
24.
Research On Yield Predicting Technique And Design For Yield
25.
ASIC Design And Implementation Of OFDM Modulation And Demodulation System
26.
IP-Core Orinted Foorplanning And Power Pad Co-optimization
27.
The Research Of Multi-objective PSO For VLSI Floorplan
28.
The Study Of ASIC Backend Design Based On SOC Encounter
29.
Floorplanning For Multi-Voltage System-on-Chips
30.
Physical Design And Optimization Of Multiplication Unit In 40 Nanometer Process
31.
A Method Of Logic Synthesis And Place-and-route For Power Balanced
32.
Physical Design Of Great Template Convolution Embedded PLL ASIC
33.
Research On Floorplan Image Recognition Based On Shape And Edge Features
34.
Back-end Design Of The Intelligent Platform Management Chip
35.
Digital Back-end Design Of RF Chip With Optimizing IR-Drop And Clock Tree
36.
A Memory-logic Separated 3D Chip Physical Design Method
37.
Timing Optimization Design Of Large-Capacity On-Chip Memory And Memory Interface Based On 28nm CMOS Technology
38.
Digital Back-end Design Of USB TYPE-C Interface Chip With Optimizing Floorplan And Placement
39.
Low Power Physical Design And Clock Tree Synthesis Of A Motor Control Chip
40.
Research On Efficient Layout Planning Scheme Based On Estimated Violations
<<First
<Prev
Next>
Last>>
Jump to
