Keyword [delay locked loop] Result: 61 - 68 | Page: 4 of 4 61.  Research And Design Of Delay Locked Loops For TDC 62.  A 200-833 MHz delay locked loop for DDR memory applications 63.  A delay-locked loop for multiple clock phases/delays generation 64.  Single event transient modeling and mitigation techniques for mixed-signal delay locked loop (DLL) and clock circuits 65.  Research On Delay-Locked Loop Based TDC ASIC In 180 Nm CMOS 66.  High Precision Digital Time Conversion Circuit 67.  Design Of Delay-Locked Loop And Research Of Radiation Hardened Key Circuits 68.  A Multiplying Delayed Phase-locked Loop With Low Jitter And Uniform Phase Separation   <<First  <Prev  Next>  Last>>  Jump to

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