Keyword [clock gating] Result: 41 - 59 | Page: 3 of 3 41.  The Design And Realization Of Power Controlling Unit For M-DSP 42.  The Research And Implementation Of Key Technology For Clock Gating Auto-Optimization On 40Gbps High Speed Serial Interface Controller 43.  Low Power Design And Verification Of A SoC Chip With Two Core 44.  Design And Implementation Of Power Management Unit (PMU) In Low-power Bluetooth Chip 45.  Low-power Technology Research And Physical Implementation Of The 28nm GPU Design 46.  The Design Of High Energy Efficiency H.264 HD Encoder 47.  The Soft Error Tolerant Latch Design Of Integrated Circuits In Nanoscale Technologies 48.  Low Power Design Of 40nm Standard Cell 49.  Power Optimization On RTL Of Memory Control Unit Based On Clock Gating Technology 50.  Design And Hardware Implementation Of Lossy Reference Frame Compression Algorithm For Low Power H.264 Coding 51.  The Research And Implementation Of Low Power Methodology Based On UPF 52.  A Display Interface Controller's Low Power Design And Evaluation 53.  Power Optimization Of PCM Module At IC Front End 54.  Research On Low Power Consumption Physical Design Based On 40nm Process MCU Chip 55.  Design of a Novel Glitch-Free Integrated Clock Gating Cell for High Reliability 56.  Power Optimization in Deep Submicron VLSI Circuits: From System Level to Circuit Leve 57.  Design Of Video Processing Module Based On Spatio-temporal Denoising Algorithm 58.  Low Power Design And Research Based On UPF 59.  The Research And Physical Design Of Low Power Technology Based On H.265 Chip   <<First  <Prev  Next>  Last>>  Jump to

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