Keyword [adder] Result: 161 - 180 | Page: 9 of 10 161.  Reliability Analysis And Fault-tolerant Design Research Of Digital Circuits 162.  Performance tradeoffs of wide-bit CMOS nanometer adder topologies with applied leakage reduction techniques 163.  An exploration of ultra-low power arithmetic supply and threshold scaling in CMOS adders 164.  The comparison between fractional-N frequency synthesizer architecture and flying-adder frequency synthesizer architecture 165.  A smart motion estimation paradigm for real-time video coding 166.  FARHAD: a Fault-Tolerant Power-Aware Hybrid Adder for High-Performance Processor 167.  A High-Speed Low-Power Modulo 2(n)+1 Multiplier Design Using Carbon-Nanotube Technology 168.  The development of an innovative adder design evaluated using programmable logic 169.  Analysis and Design of High Performance 128-bit Parallel Prefix End-Around-Carry Adder 170.  High-speed carry skip adder implemented using speculative Han-Carlson parallel prefix adder 171.  Simulation and analysis of high-speed conditional carry select adder 172.  Redundant adder architectures for cell-based technology 173.  Implementation of floating-point FPGA adder/subtractor and multiplier 174.  FPGA architecture and performance measurement for fast area efficient Parallel-Prefix modulo 2('n)-1 adders 175.  Design and implementation of low-power ASIC components 176.  Performance analysis of computation speedup in delay-insensitive dual rail logic circuits 177.  64-bit area efficient binary adder in quantum-dot cellular automata 178.  MINIMAL PARALLEL BINARY ADDERS WITH AND/OR GATES AND A SCHEME FOR A COMPACT PARALLEL MULTIPLIER 179.  A fast aynchronous approximate adder with error correction 180.  Research On Silicon Based Plasmonic Polarization Handling Devices   <<First  <Prev  Next>  Last>>  Jump to

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