Font Size:
a
A
A
Keyword [Viterbi decoder]
Result: 81 - 88 | Page: 5 of 5
81.
A fully parallel, multi-chip, long constraint length optoelectronic Viterbi decoder: Design, modeling, and analysis
82.
Design of a low power asynchronous Viterbi decoder for wireless communications
83.
VLSI implementation of a 2/3 Viterbi decoder and noise effects in digital ICs
84.
High-speed Viterbi decoder design and implementation with FPGA
85.
Hardware Architecture Design For Narrowband IoT Chip Multimode Accelerator
86.
Design And Implementation Of Seu Fault Injection Platform Based On Partial Reconfiguration Of FPGA
87.
Research And Design Of High Performance Multimode Viterbi Decoder
88.
Reliability Analysis And Fault Tolerance Design For Viterbi Decoders To SEU On User Memory
<<First
<Prev
Next>
Last>>
Jump to
