Keyword [VLSI Architecture] Result: 41 - 57 | Page: 3 of 3 41.  Low-complexity Algorithms And Implementations For Massive MIMO Detection 42.  VLSI Optimizations And Implementations For Convolutional Neural Networks 43.  Low-resource VLSI Architecture Design For Binocular Stereo Matching 44.  VLSI Architecture Design For Spiking Convolutional Neural Network 45.  Accuracy Controllable BCNN VLSI Architecture And Circuit Design For Common Word Recognition 46.  VLSI Architecture Design For Binary Convolutional Neural Network Accelerator 47.  Tree Search Based MIMO Detectors: Algorithms and VLSI Architectures 48.  VLSI architecture for a dual base multiplier 49.  A VLSI architecture for lifting-based wavelet packet transform in fingerprint image compression 50.  VLSI architecture for a 16-bit Multiply-Accumulator (MAC) operating in multiplication time 51.  Image sequence segmentation using multiple features and edge fusion: Its algorithm and VLSI architecture 52.  Reconfigurable VLSI architecture and design for digit-serial DSP applications 53.  A robust hybrid VLSI neural network architecture for a smart optical sensor 54.  VLSI architecture for a motion vision sensor 55.  VLSI architectures for video compression applications 56.  Algebraic Code Algorithms In Finite Fields And Their VLSI Architectures 57.  Circuit Design For HEVC Hierarchical Motion Estimation Algorithm   <<First  <Prev  Next>  Last>>  Jump to

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