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Keyword [Sizing]
Result: 61 - 79 | Page: 4 of 4
61.
Sizing router buffers
62.
A computational framework for automating generation of finite element mesh sizing function via skeletons
63.
Lot-sizing and scheduling problem with earliness and tardiness penalties
64.
Performance macro-modeling techniques for fast analog circuit synthesis
65.
Design methodologies for on-chip inductive interconnect
66.
Sizing database systems for business intelligence workloads
67.
Essays on scheduling and lot sizing models
68.
An integrated approach for lot sizing and scheduling problems using meta-heuristics: Genetic algorithms (GA) and simulated annealing (SA)
69.
Integrated logic and physical design for deep submicron VLSI optimization
70.
Extensions to the capacitated lot-sizing problem: A solution framework
71.
Mintime: A dynamic lot sizing and scheduling method for multiple product, single resource production systems
72.
Integrative cycle scheduling approach to discrete capacitated lot sizing and sequencing problem
73.
SIMULTANEOUS LOT SIZING AND SCHEDULING: A HEURISTIC ALGORITHM FOR DYNAMIC, DISCRETE DEMANDS ON A SINGLE FACILITY
74.
CAPACITY SENSITIVE LOT SIZING DECISIONS IN MATERIAL REQUIREMENTS PLANNING SYSTEM
75.
Net Weighting Methods and Other Novel Approaches in Variation-Aware Placement and Sizing
76.
Discrete Gate Sizing Methodologies for Delay, Area and Power Optimization
77.
Research On Variation Considered Power Optimization Method Of Near-Threshold Circuit
78.
Application Of Design Equations And Particle Swarm Optimization Method To Automatic CMOS Multi-Stage Amplifier Sizing
79.
Research On The Distribution Network Optimization With DG Based On Improved Harmonic Search Algorithm
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