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Keyword [Single Event Upset]
Result: 81 - 94 | Page: 5 of 5
81.
OPTICAL SIMULATION OF SINGLE EVENT UPSETS IN SILICON DEVICES
82.
Single event upset mechanisms in emerging memory technologies
83.
TCAD Simulation Of Single Event Latch-up And Upset Effect In FinFET Devices
84.
Research On Single Event Effect Of 3D Packaging ICS Based On TSV Interposer
85.
Study On Single-event Effect Of 28nm FDSOI Transistor And Cell Circuit
86.
Design Of Multi-node Upset Hardened Latches For Digital Integrated Circuits
87.
Research On Hardened Latch Designs For Anti-Single Event Upset In Integrated Circuits
88.
Design And SEU Hardening Of EFPGA Core For Pixel Chip
89.
Design And Research Of Hardened Latch With Multi Node Upset Tolerance In Nanoscale
90.
Research On Radiation Characteristics And Hardening Techniques Of 28 Nm SRAM Chip
91.
Design Of A Fast Fault Injection Platform For Modeling Single Event Upset On Virtex-6 FPGA
92.
Reliability Analysis And Fault Tolerance Design For Viterbi Decoders To SEU On User Memory
93.
Design And Implementation Of Configuration Memory SEU Tolerant Viterbi Decoders In SRAM Based FPGAs
94.
Research On Soft Error Detection Technology For Radiation Environment
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