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Keyword [SerDes]
Result: 41 - 60 | Page: 3 of 7
41.
Design And Realization Of A Multi-channel SFP Optical Transceiver Module Monitoring System
42.
The Key Circuits Design Of High-speed SERDES Interface
43.
High-Speed SERDES Interface Modeling And The Design Of PLL
44.
Design Of CDR And FFE In 20Gb/S High-Speed SerDes
45.
Design Of Clock Data Recovery In Serdes System
46.
Design Of Frequency-locked Loop For 12.5GB/s SerDes CDR
47.
Research On Jitter Simulation Technology Applied In High-Speed SerDes Chip
48.
Design And Implementation Of SerDes Chip Based On 8b/10b Architecture
49.
Optimal Design Of Clock And Data Recovery Circuit For 40Gb/s SerDes
50.
Design Of A 40Gb/s SerDes Transmitter Chip
51.
Design Of Phase-locked Loop Circutes For 12.5Gbps SerDes CDR
52.
Research On Verification And Testing Of SERDES Chip
53.
Design Of 40Gb/S 1:4 Demux
54.
Design Of Low Power Clock And Data Recovery Circuit Applied In SerDes Receiving System
55.
Modeling Of High Speed Serial System And Design Of Adaptive Analog Equalizer
56.
Design Of Adaptive Equalizer And VCO In High-speed SERDES
57.
Design Of PLL Frequency Multiplier Applied In 3.125 Gb/s SerDes Transmitting System
58.
Design Of CP PLL For 1.6-2.5Gbps Clock Data Recovery Circuits
59.
Design Optimization For High-Speed SerDes Physical Layer Based On High-Order Signaling Techniques
60.
Key Technologies Research Of 12.5Gb/S SerDes Receiver And High-speed Low-power Demultiplexer
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