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Keyword [On-chip test]
Result: 1 - 12 | Page: 1 of 1
1. Architecture Of Design-For-Testability And Its Optimization For System-On-Chip
2. Research On Design For Testability And Test Techniques Of Network-on-Chip System
3. The Research On NoC Test Scheduling And Mapping Method Concerning Low-Power
4. Studies On SOC Test Methodologies Based On Bus Scheduling And Buffer Addition
5. Research On Testing And Calibration Method Of S-parameters Of Microwave Planar Circuit Network
6. On-chip Network Fault Tolerance Design, Testing And Granularity Modeling
7. 100 Core Process Variation Tolerant Network On Chip Design And Many-core Granularity Modeling
8. Research On Test Data Compression Methods In SOC Based On Full Scan Design
9. Research On Optimization Method Of Testing Time And Cost Of Three-dimensional System-on-chip
10. Study of process variation in nanometer CMOS technology using multiple on chip test structures
11. Achieving optimal system-on-chip test schedules
12. Research On 3D NoC Test Planning Based On Pipeline Calculation
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