Keyword [Leakage Power] Result: 41 - 53 | Page: 3 of 3 41.  Deep sub-micron SRAM design for ultra-low leakage standby operation 42.  Design methodologies and CAD tools for leakage power optimization in FPGAs 43.  Circuit timing and leakage power analysis under process variations 44.  Estimating dynamic leakage power in digital CMOS circuits using a VHDL-based technique 45.  High-level synthesis algorithms for low power ASIC design 46.  A Power Reduction Technique Through Dynamic Runtime Algorithm For CMOS VLSI Circuits 47.  Methodology for Standby Leakage Power Reduction in Nanometer-Scale CMOS Circuits 48.  Leakage power optimization in high-performance digital circuit modules using power supply gating 49.  Design of high performance, low power VLSI circuits for scaled technologies 50.  Circuit and microarchitectural techniques for processor on-chip cache leakage power reduction 51.  Nonvolatile Cache and Flip-Flop Design for Low Standby Leakage SoC 52.  Next Generation Hardware Monitoring Infrastructure for Multi-core Resource Auditing 53.  Study And Design Of Two Port High Speed And Low Consumption SRAM   <<First  <Prev  Next>  Last>>  Jump to

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