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Keyword [High Level Synthesis]
Result: 101 - 120 | Page: 6 of 7
101.
High-level synthesis for dynamically reconfigurable systems
102.
Algorithms for design space exploration and high-level synthesis for multi-FPGA reconfigurable computers
103.
A C-based high level synthesis system
104.
Control/data path tradeoffs in high-level synthesis
105.
Investigation of neural networks for the scheduling and allocation problem in high-level synthesis
106.
High level synthesis of neural network chips
107.
Scalable and High Quality Algorithm Design For High Level Synthesis
108.
Applications of Formal And Semi-formal Verification on Software Testing, High-level Synthesis And Energy Interne
109.
Research On Reconfigurable-based Network Packet Processing And Fast Development Approach
110.
Research On Parallel Computing Architecture Of Siamese Network Algorithm
111.
Mapping Algorithm Based On Hardware Description Language
112.
Research On Neural Network Accelerator Based On PYNQ
113.
Design Of Embedded Multi-FPGAs Heterogeneous Computing System
114.
Research On Dataflow Architecture-based High Level Synthesis For Graph Processing
115.
Design And Application Of Configurable High-level Synthesis Functional Library Based On FPGA
116.
Design And Research Of FPGA-based Deep Learning Accelerator
117.
Research On Linearization Technology Of Frequency Hopping Power Amplifier Based On Orthogonal Chebyshev Polynomial
118.
Design Of High-performance JPEG Encoder Based On HLS
119.
Research On Real-time Imaging Technology Of Spaceborne SAR
120.
Path Planning Algorithm For Hardware Designed
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