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41. Design Of The Lower Power Arithmetic And Logical Unit
42. The Research & Design On 64-bit 1.47GHz High-Performance Integer Adder
43. Design And Implementation Of High Performance Low Power Embedded SRAM
44. Full Custom Design Of YHFT-DX's High Performance Computation Unit
45. The Full Custom Design And Implementation Of A 600MHz SRAM Based On 130nm Technology
46. Full Custom Design And Realization Of SRAM In L2 Cache Tag
47. Very Deep Submicron GHz CAM Full Custom Design
48. Research And Design Of The Memory Based On DSP Chip
49. The Design And Implementation Of A 600MHz Multi-port Register File
50. The Pivotal Module Physical Design Of YHFT-DX
51. Design And Implementation Of The Low-Power DSP Multiply-Add-Fused Unit
52. Research And Implementation Of High Reliability Low Power SRAM For X Microprocessor
53. Full Custom Design And Implementation Of High-Speed Register File In X Processor
54. The Design And Implemention Of DMA Controller In Embedded System-on-a-Chip
55. The High-Performance ALU Design Of Multi-Core Microprocessor
56. Design Of A Large Tuning Range And Fully Differential Phase-locked Loop For Application Of ADC Measurement
57. The Research And Implementation Of Dpa-resistant Standard Cells And Encryption Arithmetic
58. The Optimization And Physical Design Of A 600MHz YHFT-DX Instruction Fetch And Dispatch Unit
59. The Design And Verification Of Multiply Unit Of 600MHz YHFT-DX
60. Optimized Design And Physical Implementation Of The High Performance Trap Logic Unit
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