Keyword [Delay-locked] Result: 61 - 74 | Page: 4 of 4 61.  A Master-slave Delay Locked Loop With Low Jitter Applied To TDC 62.  The Design And Implementation Of A Clock Generator Based On DLL 63.  Research And Design Of Delay Locked Loops For TDC 64.  Design and analysis of jitter-tolerant digital delay-locked loops and fixed delay lines 65.  Testing embedded phase-locked loops and delay-locked loops 66.  A 200-833 MHz delay locked loop for DDR memory applications 67.  A delay-locked loop for multiple clock phases/delays generation 68.  Low jitter design techniques for monolithic CMOS phase-locked and delay-locked systems 69.  Research and design of low jitter, wide locking-range all-digital phase-locked and delay-locked loops 70.  Single event transient modeling and mitigation techniques for mixed-signal delay locked loop (DLL) and clock circuits 71.  Research On Delay-Locked Loop Based TDC ASIC In 180 Nm CMOS 72.  High Precision Digital Time Conversion Circuit 73.  Design Of Delay-Locked Loop And Research Of Radiation Hardened Key Circuits 74.  A Multiplying Delayed Phase-locked Loop With Low Jitter And Uniform Phase Separation   <<First  <Prev  Next>  Last>>  Jump to

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