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Keyword [Deep Sub-micron]
Result: 61 - 77 | Page: 4 of 4
61.
Power and clock distribution networks optimization for deep sub-micron designs
62.
RF receiver front-ends in deep sub-micron CMOS for mobile terminal
63.
Noise analysis and design methodologies in deep sub-micron VLSI circuits
64.
Design flow for deep sub-micron integrated-circuits
65.
Interconnect modeling, signal integrity and reliability analysis for deep sub-micron integrated circuits
66.
Novel methodologies to improve signal integrity of precharge-evaluate circuits in deep sub-micron regime
67.
RF power amplifier using deep sub-micron CMOS technology
68.
High field/high current reliability issues for deep sub-micron CMOS
69.
Modeling, testing and analysis for delay defects and noise effects in deep sub-micron devices
70.
New dynamic power supply current testing methodologies for very deep sub-micron CMOS circuits
71.
Power supply noise analysis for deep sub-micron (DSM) VLSI circuits
72.
Interconnect optimization in deep sub-micron design under the transmission line model
73.
Accurate gate delay evaluation of CMOS deep sub-micron VLSI circuits
74.
Oxynitride gate dielectrics for deep sub-micron MOS devices
75.
Three-dimensional particle-based simulations of deep sub-micron MOSFET devices
76.
Deep sub-micron MOS transistor design and manufacturing sensitivity analysis
77.
Timing Analysis And Simulation Of Nano-Integrated Circuits Considering The Fluctuation Of Power Supply Network
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