Deep Sub-micron - Globe Thesis

Keyword [Deep Sub-micron] Result: 41 - 60 \| Page: 3 of 4
41.	The Reconfigurable Chip Clock Tree Synthesis Technology Based On65nm
42.	Temperature Modeling Of Total Ionizing Dose Effect In Deep Sub-micron CMOS
43.	Research On ESD Protection Improvement And Application For MCU Circuits On0.35um Process
44.	Optimizationand Trade-off Analysis In The Physical Design Of Deep Sub-micron IC
45.	Research On CMOS Time-to-Digital Converter In Deep Sub-micron CMOS
46.	Study On Radiation Mechanism And Simulation Technology Of Deep Sub-micron Devices
47.	Deep Sub-Micron MOSFET Nonlinear Capacitance Modeling Techniques Study
48.	Spectral Element Method Analysis Of Transient Electrothermal Characteristics Of Deep Submicron Semiconductor Devices
49.	Runtime leakage control in deep sub-micron CMOS technologies
50.	Inter-Module Interfacing Techniques for SoCs with Multiple Clock Domains to Address Challenges in Modern Deep Sub-Micron Technologies
51.	Digitally calibrated analog-to-digital converters in deep sub-micron CMOS
52.	Deep sub-micron SRAM design for ultra-low leakage standby operation
53.	Nanoscale stresses simulation and characterization of deep sub-micron semiconductor devices
54.	High Performance SAR-based ADC Design in Deep Sub-micron CMOS
55.	Energy efficient design for deep sub-micron CMOS VLSIs
56.	Current-based test in deep sub-micron environment
57.	Design Techniques for Power-efficient Data Converters in Deep Sub-micron CMOS Technologies
58.	High-performance SOI pseudo-nMOS circuit design techniques for the deep sub-micron era
59.	A power optimized pipelined analog-to-digital converter design in deep sub-micron CMOS technology
60.	Modeling and mitigation of radiation-induced charge sharing effects in advanced electronics
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