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Keyword [Cores]
Result: 101 - 120 | Page: 6 of 8
101.
The velocity compiler: Extracting efficient multicore execution from legacy sequential codes
102.
Runtime allocation and scheduling policies across network on chip architectures
103.
Parallel subgraph mining on hybrid platforms: HPC systems, multi-cores and GPUs
104.
Memory interface architecture for network on chip based systems
105.
Optimizing Throughput and Power Consumption of Graphics Processing Units (GPUs)
106.
Holistic design for multi-core architectures
107.
Erie lobe fine-grained till in northeastern Indiana: Insights into Lagro stratigraphy and depositional mechanisms from cores in the Wabash moraine
108.
Statistical machine learning based modeling framework for design space exploration and run-time cross-stack energy optimization for many-core processors
109.
Exploiting properties of CMP cache traffic in designing hybrid packet/circuit switched NoCs
110.
Micronetwork based system-on-FPGA (SoFPGA) architecture
111.
Energy-Efficient and High-Performance Nanophotonic Interconnects for Shared Memory Multicores
112.
Architecting a Workload-agnostic Heterogeneous Multi-core Processor
113.
SOC test scheduling with hot-spot avoidance based on user-defined constraints
114.
Test infrastructure design for digital, mixed-signal, and hierarchical SOCs
115.
Layout conscious approach and bus architecture synthesis for hardware-software co-design of systems on chip optimized for speed and power
116.
Hardware and software co-design in space compaction of cores-based digital circuit
117.
Exploiting heterogeneous multicore processors through fine-grained scheduling and low-overhead thread migration
118.
Configurable Energy-efficient Co-processors to Scale the Utilization Wall
119.
Design and implementation of clocked Open Core Protocol interfaces for Intellectual Property cores and on-chip network fabric
120.
Reducing interference in memory hierarchy resources using application aware management
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