Clock and Data Recovery - Globe Thesis

Keyword [Clock and Data Recovery] Result: 61 - 80 \| Page: 4 of 5
61.	Burst-mode clock and data recovery circuits for optical multiaccess networks
62.	Design of noise-robust clock and data recovery using an adaptive-bandwidth mixed PLL/DLL
63.	Novel techniques to increase capture range of clock and data recovery circuit
64.	Novel systematic phase noise reduction techniques for phase interpolator clock and data recovery
65.	Design of a broadband PLL solution for burst-mode Clock and Data Recovery in all-optical networks
66.	An inductively tuned silicon germanide BiCMOS quadrature VCO for clock and data recovery applications
67.	Clock and data recovery for high-speed ADC-based receivers
68.	Clock and data recovery circuits
69.	Gigabit/second clock and data recovery circuits for local area networks
70.	Design and modeling of high-speed clock and data recovery circuits
71.	High-speed clock and data recovery circuits in CMOS technology
72.	Design considerations for high-speed clock and data recovery circuits
73.	High-speed clock and data recovery circuits for random non-return-to-zero data
74.	A 10-Gb/s CMOS clock and data recovery circuit
75.	Delay flip-flop (DFF) metastability impact on clock and data recovery (CDR) and phase-locked loop (PLL) circuits
76.	Phase locked loop (PLL) - based clock and data recovery circuit (CDR) using calibrated delay flip flop (DFF)
77.	Research On Key Technologies Of High-speed And Low-power Wireline Serial Receiver Supporting Multiple Standards
78.	SerDes Interface Circuit Design Of Gigabit Ethernet
79.	Research On Clock And Data Recovery Circuit For High Speed SerDes
80.	Design Of Clock And Data Recovery Circuit For 40Gb/s Serdes
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