Keyword [Clock Tree] Result: 61 - 78 | Page: 4 of 4 61.  Research On Clock Network Optimization Based On 55nm Process ASIC Chip 62.  Algorithms and methodology in physical domain optimization for high-performance VLSI design 63.  Clock tree analysis and synthesis considering process parameters and variability 64.  Post route clock tree analysis at multi-GHz with inductance effect 65.  Algorithms for interconnect planning and optimization in deep-submicron VLSI design 66.  Clock tree synthesis for low-power IC design 67.  Digital Back-end Design Of LPDDR3 Physical Interface 68.  Design Of The Buffering Strategy For Clock Trees Under Near-Threshold-Voltage 69.  Design Of A Balanced Clock Tree Synthesis For Clock Skew Optimizations Under Near-threshold Voltages 70.  Research And Implementation Of Key Techniques In 3D Clock Tree Synthesis For Noise Avoidance 71.  Analysis And Optimization Of Signal Crosstalk In 3D Clock Tree Synthesis 72.  Research And Design Of Digital Back-end Based On Anti-radiation SRAM 73.  Dynamic Reconfigurable Clock Tree Design Methodology For Wide Voltage Scaling 74.  Register Grouping Design For Anti-process Variation Clock Tree Under Near-threshold 75.  Research On Key Techniques Of Low Power Double Edge Triggered Flip-flop Design With Blocking Glitches 76.  Back-end Design Of GPU Core Computing Unit Based On 7nm Technology 77.  Physical Design Of FT-DMx High-performance Anti-irradiation DSP Core 78.  Research On Ultra-short Shutter Time X-ray CMOS Image Sensor   <<First  <Prev  Next>  Last>>  Jump to

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