Charge pump phase-locked loop - Globe Thesis

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Keyword [Charge pump phase-locked loop] Result: 21 - 40 \| Page: 2 of 4
21.	Design Of Charge-Pump Phase Locked Loop In Micro-Inertial
22.	Analysis And Design Of Low-Noise Charge-Pump PLL
23.	The Research And Design Of CMOS Charge-Pump Phase-Locked Loop
24.	The Design Of Cmos Charge Pump Phase-locked Loop Circuit
25.	The Realization Of Charge Pump Phase-locked Loop Frequency Synthesizer
26.	The Circuit Design Of Physical Layer Of USB2.0 Transceiver
27.	Research And Implementation Of The Analog Circuit In The DVI Receiver
28.	Design Of A CMOS Charge Pump Phase Locked Loop
29.	Design Of A Novel Charge Pump Phase-locked Loop
30.	Design Of PFD And CP In PLL
31.	The Design Of 1.5-3.0GHz Charge Pump Phase Locked Loop Based On 40nm CMOS
32.	Design Of A 40Gb/s SerDes Transmitter Chip
33.	Design Of PLL Frequency Multiplier Applied In 3.125 Gb/s SerDes Transmitting System
34.	The Research And Design Of Fast Lock Charge Pump Phase Locked Loop
35.	Design Of CPPLL Applied In High Speed Circuit
36.	Research And Design Of An Programmable CMOS Integrated Charge Pump Phase-locked Loop
37.	Research And Design Of CPPLL Based On Fractional-N Divider
38.	Design Of High-speed CMOS Charge Pump Phase-locked Loop
39.	Research And Design Of Fast Locking And Low Jitter Charge Pump Phase Locked Loop
40.	Used In Serial Communication Equipment In The Research Of Low Noise Charge Pump Phase-locked Loop
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