Research On A Digital Correlated Double Sampling Circuit Based On A Low Power SAR/SS ADC

The development of intelligent medicine,outdoor medicine and telemedicine has put forward the demand for portable and miniaturized cell detection system.The cell microscopic imaging detection system based on CMOS image sensor and microfluidic technology makes this demand possible.CMOS image sensor,especially its readout circuit,is the main power source of the detection system.In addition,the heat dissipation of the chip will also affect the results of cell detection.Therefore,the research on the high-speed,high-precision and low-power readout circuit of CMOS image sensor is of great significance for the microscopic imaging system.Aiming at the requirements of portable cell imaging detection system,this paper studies the low power SAR/SS ADC used for CMOS image sensor and the digital correlation double sampling circuit based on the ADC,which can achieve high speed and high precision conversion while reducing the system power consumption.Firstly,a 12-position two-step SAR/SS ADC is designed.The ADC is divided into a high 5-bit SAR quantization process and a low 7-bit SS quantization process to obtain high speed and high precision.The ADC is mainly composed of a grid voltage boot-up switch,comparator,capacitor DAC,SAR logic,ramp generator,counter and register.The comparator is composed of a latch and output buffer circuit.The capacitor DAC uses VREF/2 and VREF as references to halve the area of the high capacitance array.Part of the DFF of SAR logic is replaced by Latch to reduce the number of transistors,thereby reducing the area needed for column circuit applications while reducing power consumption.At the same time,the sampling switch in this paper adopts a grid voltage bootstrap structure to improve the sampling linearity of ADC,and a self-calibrating integral ramp generator is used to provide high precision ramp voltage for ADC low quantization.Then,this paper studies a low power digital correlation double sampling circuit based on the proposed low power SAR/SS ADC.The pixel integrated signal is quantized by a two-step SAR/SS ADC,while the pixel reset signal is quantized by using the low position of the SAR/SS ADC,and the high position quantization step of the pixel reset signal is ignored to reduce the circuit power consumption.The low power quantization method proposed in this paper can realize the double sampling count by using DOWN counter,which avoids the traditional SS AdC-based digital correlation double sampling circuit that needs to add a selector to realize the UP/DOWN function,and further reduces the circuit area and power consumption.In addition,the proposed high level digital correlation double sampling circuit is implemented by subtracter,and a high level redundant bit is added to the low level counter,the calculation is based on the output of the low-level correlated dual sampler circuit.The digital correlation dual-sampling circuit based on low power SAR/SS ADC proposed in this paper is implemented by UMC110nm technology,and the power supply voltage of analog and digital circuits is 3.3V and 1.2V respectively.The schematic design,layout design and simulation verification of ADC and digital correlation dual-sampling circuit are carried out using Cadence platform.The simulation results show that DNL and INL of the circuit are+0.4/-0.5LSB and+0.5/-0.6LSB,respectively.When sampling 14kHz input signal at the sampling frequency of 142kS/s,ENOB is 10.82bit,SFDR is 87.5dB,THD is-80.2dB.The SNR and SNDR are 67.2dB and 67dB respectively.The power consumption and area of the single-column circuit are 70.25μW and 10μm× 1367.4μm respectively.